* [dpdk-dev] [PATCH 1/2] common/cnxk: fix ROC naming convention issues
@ 2022-03-17 3:50 psatheesh
2022-03-17 3:50 ` [dpdk-dev] [PATCH 2/2] common/cnxk: fix QINQ ROC item mismatch issue psatheesh
2022-04-25 5:11 ` [dpdk-dev] [PATCH 1/2] common/cnxk: fix ROC naming convention issues Jerin Jacob
0 siblings, 2 replies; 3+ messages in thread
From: psatheesh @ 2022-03-17 3:50 UTC (permalink / raw)
To: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
Cc: dev, Satheesh Paul, stable
From: Satheesh Paul <psatheesh@marvell.com>
Fixed some names to follow ROC naming convention in ROC NPC code.
Fixes: 4edf1246a40 ("common/cnxk: support matching VLAN existence in RTE Flow")
Cc: stable@dpdk.org
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
---
drivers/common/cnxk/roc_npc.h | 6 +++---
drivers/common/cnxk/roc_npc_mcam.c | 4 ++--
drivers/common/cnxk/roc_platform.h | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h
index 6204139396..4c0151e2e7 100644
--- a/drivers/common/cnxk/roc_npc.h
+++ b/drivers/common/cnxk/roc_npc.h
@@ -60,7 +60,7 @@ struct roc_npc_flow_item_raw {
struct roc_ether_addr {
uint8_t addr_bytes[PLT_ETHER_ADDR_LEN]; /**< Addr bytes in tx order */
-} plt_aligned(2);
+} __plt_aligned(2);
struct roc_ether_hdr {
struct roc_ether_addr d_addr; /**< Destination address. */
@@ -72,7 +72,7 @@ struct roc_ether_hdr {
} S_un; /**< Do not use directly; use s_addr instead.*/
};
uint16_t ether_type; /**< Frame type. */
-} plt_aligned(2);
+} __plt_aligned(2);
PLT_STD_C11
struct roc_npc_flow_item_eth {
@@ -254,7 +254,7 @@ enum roc_npc_rss_hash_function {
struct roc_npc_action_rss {
enum roc_npc_rss_hash_function func;
uint32_t level;
- uint64_t types; /**< Specific RSS hash types (see RTE_ETH_RSS_*). */
+ uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
uint32_t key_len; /**< Hash key length in bytes. */
uint32_t queue_num; /**< Number of entries in @p queue. */
const uint8_t *key; /**< Hash key. */
diff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c
index 9c5ff5e60a..e592310bde 100644
--- a/drivers/common/cnxk/roc_npc_mcam.c
+++ b/drivers/common/cnxk/roc_npc_mcam.c
@@ -283,8 +283,8 @@ npc_get_kex_capability(struct npc *npc)
/* Custom L3 frame: varied offset and lengths */
kex_cap.bit.custom_l3 =
npc_is_kex_enabled(npc, NPC_LID_LC, NPC_LT_LC_CUSTOM0, 0, 0);
- kex_cap.bit.custom_l3 |=
- npc_is_kex_enabled(npc, NPC_LID_LC, NPC_LT_LC_CUSTOM1, 0, 0);
+ kex_cap.bit.custom_l3 |= (uint64_t)npc_is_kex_enabled(
+ npc, NPC_LID_LC, NPC_LT_LC_CUSTOM1, 0, 0);
/* SCTP sport : offset 0B, len 2B */
kex_cap.bit.sctp_sport = npc_is_kex_enabled(
npc, NPC_LID_LD, NPC_LT_LD_SCTP, 0 * 8, 2 * 8);
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index 28004b1743..dd6514eb10 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -98,7 +98,7 @@
#define plt_cpu_to_be_64 rte_cpu_to_be_64
#define plt_be_to_cpu_64 rte_be_to_cpu_64
-#define plt_aligned __rte_aligned
+#define __plt_aligned __rte_aligned
#define plt_align32pow2 rte_align32pow2
#define plt_align32prevpow2 rte_align32prevpow2
--
2.25.4
^ permalink raw reply [flat|nested] 3+ messages in thread
* [dpdk-dev] [PATCH 2/2] common/cnxk: fix QINQ ROC item mismatch issue
2022-03-17 3:50 [dpdk-dev] [PATCH 1/2] common/cnxk: fix ROC naming convention issues psatheesh
@ 2022-03-17 3:50 ` psatheesh
2022-04-25 5:11 ` [dpdk-dev] [PATCH 1/2] common/cnxk: fix ROC naming convention issues Jerin Jacob
1 sibling, 0 replies; 3+ messages in thread
From: psatheesh @ 2022-03-17 3:50 UTC (permalink / raw)
To: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
Cc: dev, Satheesh Paul, stable
From: Satheesh Paul <psatheesh@marvell.com>
ROC code is assuming presence of vlan extension headers in
case of QINQ, because of this, there is incompatibility
between the driver and ROC. Fixed this issue.
Fixes: 4edf1246a40 ("common/cnxk: support matching VLAN existence in RTE Flow")
Cc: stable@dpdk.org
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
---
drivers/common/cnxk/roc_npc_parse.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/common/cnxk/roc_npc_parse.c b/drivers/common/cnxk/roc_npc_parse.c
index b849326a19..757bff29a7 100644
--- a/drivers/common/cnxk/roc_npc_parse.c
+++ b/drivers/common/cnxk/roc_npc_parse.c
@@ -337,15 +337,10 @@ npc_parse_lb(struct npc_parse_state *pst)
}
info.len = pattern->size;
} else if (pst->pattern->type == ROC_NPC_ITEM_TYPE_QINQ) {
- vlan_item[0] = pst->pattern->spec;
info.hw_mask = NULL;
- info.len = sizeof(vlan_item[0]->hdr);
+ info.len = pattern->size;
lt = NPC_LT_LB_STAG_QINQ;
lflags = NPC_F_STAG_CTAG;
- if (vlan_item[0] && vlan_item[0]->has_more_vlan) {
- lflags = NPC_F_LB_L_WITH_QINQ_CTAG &
- NPC_F_LB_L_WITH_QINQ_QINQ;
- }
} else if (pst->pattern->type == ROC_NPC_ITEM_TYPE_RAW) {
raw_spec = pst->pattern->spec;
if (raw_spec->relative)
--
2.25.4
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [dpdk-dev] [PATCH 1/2] common/cnxk: fix ROC naming convention issues
2022-03-17 3:50 [dpdk-dev] [PATCH 1/2] common/cnxk: fix ROC naming convention issues psatheesh
2022-03-17 3:50 ` [dpdk-dev] [PATCH 2/2] common/cnxk: fix QINQ ROC item mismatch issue psatheesh
@ 2022-04-25 5:11 ` Jerin Jacob
1 sibling, 0 replies; 3+ messages in thread
From: Jerin Jacob @ 2022-04-25 5:11 UTC (permalink / raw)
To: Satheesh Paul, ferruh.yigit, Andrew Rybchenko
Cc: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao,
dpdk-dev, dpdk stable
On Thu, Mar 17, 2022 at 9:21 AM <psatheesh@marvell.com> wrote:
>
> From: Satheesh Paul <psatheesh@marvell.com>
>
> Fixed some names to follow ROC naming convention in ROC NPC code.
>
> Fixes: 4edf1246a40 ("common/cnxk: support matching VLAN existence in RTE Flow")
> Cc: stable@dpdk.org
>
> Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Series Acked-by: Jerin Jacob <jerinj@marvell.com>
Updated the git commit as follows and applied to
dpdk-next-net-mrvl/for-next-net. Thanks
commit 4ca662394ed53a6c7c658d84095b4095542c542c (HEAD -> for-next-net,
origin/for-next-net)
Author: Satheesh Paul <psatheesh@marvell.com>
Date: Thu Mar 17 09:20:36 2022 +0530
common/cnxk: fix QinQ ROC item mismatch
ROC code is assuming presence of vlan extension headers in
case of QinQ, because of this, there is incompatibility
between the driver and ROC. Fixed this in ROC by treating
QINQ as multiple VLAN pattern items for DPDK (as opposed to
treating QINQ as separate pattern item).
Fixes: b8ac8b089ce ("common/cnxk: support matching VLAN existence")
Cc: stable@dpdk.org
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
commit 259aa7ab9040d6275783e3a90cb711a2e7573ab1
Author: Satheesh Paul <psatheesh@marvell.com>
Date: Thu Mar 17 09:20:35 2022 +0530
common/cnxk: correct ROC naming conventions
Corrected some names to follow ROC naming convention in ROC NPC code.
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
> ---
> drivers/common/cnxk/roc_npc.h | 6 +++---
> drivers/common/cnxk/roc_npc_mcam.c | 4 ++--
> drivers/common/cnxk/roc_platform.h | 2 +-
> 3 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h
> index 6204139396..4c0151e2e7 100644
> --- a/drivers/common/cnxk/roc_npc.h
> +++ b/drivers/common/cnxk/roc_npc.h
> @@ -60,7 +60,7 @@ struct roc_npc_flow_item_raw {
>
> struct roc_ether_addr {
> uint8_t addr_bytes[PLT_ETHER_ADDR_LEN]; /**< Addr bytes in tx order */
> -} plt_aligned(2);
> +} __plt_aligned(2);
>
> struct roc_ether_hdr {
> struct roc_ether_addr d_addr; /**< Destination address. */
> @@ -72,7 +72,7 @@ struct roc_ether_hdr {
> } S_un; /**< Do not use directly; use s_addr instead.*/
> };
> uint16_t ether_type; /**< Frame type. */
> -} plt_aligned(2);
> +} __plt_aligned(2);
>
> PLT_STD_C11
> struct roc_npc_flow_item_eth {
> @@ -254,7 +254,7 @@ enum roc_npc_rss_hash_function {
> struct roc_npc_action_rss {
> enum roc_npc_rss_hash_function func;
> uint32_t level;
> - uint64_t types; /**< Specific RSS hash types (see RTE_ETH_RSS_*). */
> + uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */
> uint32_t key_len; /**< Hash key length in bytes. */
> uint32_t queue_num; /**< Number of entries in @p queue. */
> const uint8_t *key; /**< Hash key. */
> diff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c
> index 9c5ff5e60a..e592310bde 100644
> --- a/drivers/common/cnxk/roc_npc_mcam.c
> +++ b/drivers/common/cnxk/roc_npc_mcam.c
> @@ -283,8 +283,8 @@ npc_get_kex_capability(struct npc *npc)
> /* Custom L3 frame: varied offset and lengths */
> kex_cap.bit.custom_l3 =
> npc_is_kex_enabled(npc, NPC_LID_LC, NPC_LT_LC_CUSTOM0, 0, 0);
> - kex_cap.bit.custom_l3 |=
> - npc_is_kex_enabled(npc, NPC_LID_LC, NPC_LT_LC_CUSTOM1, 0, 0);
> + kex_cap.bit.custom_l3 |= (uint64_t)npc_is_kex_enabled(
> + npc, NPC_LID_LC, NPC_LT_LC_CUSTOM1, 0, 0);
> /* SCTP sport : offset 0B, len 2B */
> kex_cap.bit.sctp_sport = npc_is_kex_enabled(
> npc, NPC_LID_LD, NPC_LT_LD_SCTP, 0 * 8, 2 * 8);
> diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
> index 28004b1743..dd6514eb10 100644
> --- a/drivers/common/cnxk/roc_platform.h
> +++ b/drivers/common/cnxk/roc_platform.h
> @@ -98,7 +98,7 @@
> #define plt_cpu_to_be_64 rte_cpu_to_be_64
> #define plt_be_to_cpu_64 rte_be_to_cpu_64
>
> -#define plt_aligned __rte_aligned
> +#define __plt_aligned __rte_aligned
> #define plt_align32pow2 rte_align32pow2
> #define plt_align32prevpow2 rte_align32prevpow2
>
> --
> 2.25.4
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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