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References: <20221208201806.21893-1-syalavarthi@marvell.com>
 <20221220192645.14042-1-syalavarthi@marvell.com>
 <20221220132357.26a8d75f@hermes.local>
In-Reply-To: <20221220132357.26a8d75f@hermes.local>
From: Jerin Jacob <jerinjacobk@gmail.com>
Date: Wed, 21 Dec 2022 10:14:25 +0530
Message-ID: <CALBAE1PoXZHtaWoaaoMS0HFXXV=5Q9SPEF_bMXvBnzRLSHeiXw@mail.gmail.com>
Subject: Re: [PATCH v3 00/38] Implementation of ML CNXK driver
To: Stephen Hemminger <stephen@networkplumber.org>
Cc: Srikanth Yalavarthi <syalavarthi@marvell.com>, dev@dpdk.org,
 sshankarnara@marvell.com, jerinj@marvell.com, aprabhu@marvell.com
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On Wed, Dec 21, 2022 at 2:54 AM Stephen Hemminger
<stephen@networkplumber.org> wrote:
>
> On Tue, 20 Dec 2022 11:26:07 -0800
> Srikanth Yalavarthi <syalavarthi@marvell.com> wrote:
>
> > Marvell ML CNXK Driver
> > ----------------------
> >
> > This patch series implements common Machine Learning (ML) ROC code
> > and driver for Marvell Octeon 10 (cnxk) platform. ML inferencing is
> > supported on cnxk platform through an integrated ML inferencing
> > processor. The current driver supports programming the ML hardware
> > engine through offload mode.
> >
> > All APIs proposed in the DPDK ML device specification are supported on
> > the cnxk platform.
>
>
> Is this hardware in the DPDK CI lab?

No

> How can the project make sure this isn't broken in future?

It will be like the rest of 95% HWs of DPDK drivers. i.e. Vendor will
make sure it is not broken.