From: Jerin Jacob <jerinjacobk@gmail.com>
To: Rahul Bhansali <rbhansali@marvell.com>,
Thomas Monjalon <thomas@monjalon.net>
Cc: dpdk-dev <dev@dpdk.org>,
Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>,
Pavan Nikhilesh <pbhagavatula@marvell.com>,
Shijith Thotton <sthotton@marvell.com>,
Ashwin Sekhar T K <asekhar@marvell.com>,
Jerin Jacob <jerinj@marvell.com>
Subject: Re: [PATCH v2] common/cnxk: add CN103XX platform support
Date: Mon, 2 May 2022 21:54:29 +0530 [thread overview]
Message-ID: <CALBAE1Psgyj_E-FHAfi9YHV7TX4asV+Rh-6s7xGvKnZvJ-ZLsg@mail.gmail.com> (raw)
In-Reply-To: <20220502113111.543873-1-rbhansali@marvell.com>
On Mon, May 2, 2022 at 5:01 PM Rahul Bhansali <rbhansali@marvell.com> wrote:
>
> Added support for CN103XX (cn10kb) platform.
>
> Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Deligating to @Thomas Monjalon as it is touching all the drivers to
update PCI ID.
> ---
> Changes in v2: squash all patches of series into one.
>
> doc/guides/platform/cnxk.rst | 1 +
> drivers/common/cnxk/roc_constants.h | 1 +
> drivers/common/cnxk/roc_model.c | 4 ++++
> drivers/common/cnxk/roc_model.h | 11 ++++++++++-
> drivers/event/cnxk/cn10k_eventdev.c | 2 ++
> drivers/mempool/cnxk/cnxk_mempool.c | 2 ++
> drivers/net/cnxk/cn10k_ethdev.c | 3 +++
> 7 files changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
> index 3dee725ac5..92aa702a78 100644
> --- a/doc/guides/platform/cnxk.rst
> +++ b/doc/guides/platform/cnxk.rst
> @@ -18,6 +18,7 @@ Supported OCTEON cnxk SoCs
> - CN98xx
> - CN106xx
> - CNF105xx
> +- CN103XX
>
> Resource Virtualization Unit architecture
> -----------------------------------------
> diff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h
> index 38e2087a26..1daaabfe55 100644
> --- a/drivers/common/cnxk/roc_constants.h
> +++ b/drivers/common/cnxk/roc_constants.h
> @@ -52,6 +52,7 @@
> #define PCI_SUBSYSTEM_DEVID_CN10KA 0xB900
> #define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900
> #define PCI_SUBSYSTEM_DEVID_CNF10KA 0xBA00
> +#define PCI_SUBSYSTEM_DEVID_CN10KB 0xB900
>
> #define PCI_SUBSYSTEM_DEVID_CN9KA 0x0000
> #define PCI_SUBSYSTEM_DEVID_CN9KB 0xb400
> diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
> index 4120029541..1dd374e0fd 100644
> --- a/drivers/common/cnxk/roc_model.c
> +++ b/drivers/common/cnxk/roc_model.c
> @@ -16,6 +16,7 @@ struct roc_model *roc_model;
> #define PART_106xx 0xB9
> #define PART_105xx 0xBA
> #define PART_105xxN 0xBC
> +#define PART_103xx 0xBE
> #define PART_98xx 0xB1
> #define PART_96xx 0xB2
> #define PART_95xx 0xB3
> @@ -46,6 +47,7 @@ static const struct model_db {
> } model_db[] = {
> {VENDOR_ARM, PART_106xx, 0, 0, ROC_MODEL_CN106xx_A0, "cn10ka_a0"},
> {VENDOR_ARM, PART_105xx, 0, 0, ROC_MODEL_CNF105xx_A0, "cnf10ka_a0"},
> + {VENDOR_ARM, PART_103xx, 0, 0, ROC_MODEL_CN103xx_A0, "cn10kb_a0"},
> {VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"},
> {VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"},
> {VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"},
> @@ -92,6 +94,8 @@ cn10k_part_get(void)
> soc = PART_105xx;
> } else if (strcmp("cnf10kb", ptr) == 0) {
> soc = PART_105xxN;
> + } else if (strcmp("cn10kb", ptr) == 0) {
> + soc = PART_103xx;
> } else {
> plt_err("Unidentified 'CPU compatible': <%s>", ptr);
> goto fclose;
> diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h
> index 4567566169..885c3d668f 100644
> --- a/drivers/common/cnxk/roc_model.h
> +++ b/drivers/common/cnxk/roc_model.h
> @@ -24,6 +24,7 @@ struct roc_model {
> #define ROC_MODEL_CN106xx_A0 BIT_ULL(20)
> #define ROC_MODEL_CNF105xx_A0 BIT_ULL(21)
> #define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22)
> +#define ROC_MODEL_CN103xx_A0 BIT_ULL(23)
> /* Following flags describe platform code is running on */
> #define ROC_ENV_HW BIT_ULL(61)
> #define ROC_ENV_EMUL BIT_ULL(62)
> @@ -50,8 +51,10 @@ struct roc_model {
> #define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0)
> #define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0)
> #define ROC_MODEL_CNF105xxN (ROC_MODEL_CNF105xxN_A0)
> +#define ROC_MODEL_CN103xx (ROC_MODEL_CN103xx_A0)
> #define ROC_MODEL_CN10K \
> - (ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN)
> + (ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN | \
> + ROC_MODEL_CN103xx)
> #define ROC_MODEL_CNF10K (ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN)
>
> /* Runtime variants */
> @@ -152,6 +155,12 @@ roc_model_is_cnf10kb(void)
> return roc_model->flag & ROC_MODEL_CNF105xxN;
> }
>
> +static inline uint64_t
> +roc_model_is_cn10kb_a0(void)
> +{
> + return roc_model->flag & ROC_MODEL_CN103xx_A0;
> +}
> +
> static inline uint64_t
> roc_model_is_cn10ka_a0(void)
> {
> diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c
> index 9b4d2895ec..75c748f611 100644
> --- a/drivers/event/cnxk/cn10k_eventdev.c
> +++ b/drivers/event/cnxk/cn10k_eventdev.c
> @@ -935,9 +935,11 @@ static const struct rte_pci_id cn10k_pci_sso_map[] = {
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
> + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KB, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
> + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KB, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
> {
> .vendor_id = 0,
> },
> diff --git a/drivers/mempool/cnxk/cnxk_mempool.c b/drivers/mempool/cnxk/cnxk_mempool.c
> index ea473552dd..a28fe5406d 100644
> --- a/drivers/mempool/cnxk/cnxk_mempool.c
> +++ b/drivers/mempool/cnxk/cnxk_mempool.c
> @@ -163,6 +163,7 @@ npa_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
> static const struct rte_pci_id npa_pci_map[] = {
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_NPA_PF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_NPA_PF),
> + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KB, PCI_DEVID_CNXK_RVU_NPA_PF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_NPA_PF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_NPA_PF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_NPA_PF),
> @@ -170,6 +171,7 @@ static const struct rte_pci_id npa_pci_map[] = {
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_NPA_PF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_NPA_VF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_NPA_VF),
> + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KB, PCI_DEVID_CNXK_RVU_NPA_VF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_NPA_VF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_NPA_VF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_NPA_VF),
> diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
> index 15dbea2180..ce3707be6f 100644
> --- a/drivers/net/cnxk/cn10k_ethdev.c
> +++ b/drivers/net/cnxk/cn10k_ethdev.c
> @@ -795,12 +795,15 @@ static const struct rte_pci_id cn10k_pci_nix_map[] = {
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_PF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_PF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_PF),
> + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KB, PCI_DEVID_CNXK_RVU_PF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_VF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_VF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_VF),
> + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KB, PCI_DEVID_CNXK_RVU_VF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_AF_VF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_AF_VF),
> CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CNF10KA, PCI_DEVID_CNXK_RVU_AF_VF),
> + CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KB, PCI_DEVID_CNXK_RVU_AF_VF),
> {
> .vendor_id = 0,
> },
> --
> 2.25.1
>
next prev parent reply other threads:[~2022-05-02 16:24 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-25 13:03 [PATCH 1/4] " Rahul Bhansali
2022-03-25 13:03 ` [PATCH 2/4] net/cnxk: " Rahul Bhansali
2022-03-25 13:03 ` [PATCH 3/4] event/cnxk: " Rahul Bhansali
2022-03-25 13:03 ` [PATCH 4/4] mempool/cnxk: " Rahul Bhansali
2022-05-01 13:45 ` [PATCH 1/4] common/cnxk: " Jerin Jacob
2022-05-02 11:31 ` [PATCH v2] " Rahul Bhansali
2022-05-02 16:24 ` Jerin Jacob [this message]
2022-05-24 5:02 ` [EXT] " Rahul Bhansali
2022-06-01 19:59 ` Thomas Monjalon
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