From: "Stanisław Kardach" <kda@semihalf.com>
To: David Marchand <david.marchand@redhat.com>
Cc: christian.ehrhardt@canonical.com, dev <dev@dpdk.org>,
Thomas Monjalon <thomas@monjalon.net>,
Luca Boccassi <bluca@debian.org>,
Bruce Richardson <bruce.richardson@intel.com>
Subject: Re: [PATCH] build: riscv is not a valid -march value
Date: Fri, 5 Jan 2024 16:50:50 +0100 [thread overview]
Message-ID: <CALVGJW+C-7wKBNraiM7_S4i87o+Y10+i7CGZ_M5_+LaVXSLU0g@mail.gmail.com> (raw)
In-Reply-To: <CAJFAV8xpMfRgNnnPuNA6j0sreU2cx0rk5X6GYNe_uLLELh1LGw@mail.gmail.com>
On Wed, Nov 22, 2023 at 5:41 PM David Marchand
<david.marchand@redhat.com> wrote:
>
> On Wed, Nov 22, 2023 at 5:17 PM Bruce Richardson
> <bruce.richardson@intel.com> wrote:
> >
> > On Wed, Nov 22, 2023 at 05:02:56PM +0100, David Marchand wrote:
> > > On Tue, Nov 21, 2023 at 5:49 PM <christian.ehrhardt@canonical.com> wrote:
> > > >
> > > > From: Christian Ehrhardt <christian.ehrhardt@canonical.com>
> > > >
> > > > If building riscv natively with -Dplatform=generic config/meson.build
> > > > will select cpu_instruction_set=riscv.
> > > >
> > > > That was fine because config/riscv/meson.build did override it to valid
> > > > values later, but since b7676fcccab4 ("config: verify machine arch
> > > > flag") it will break the build as it tries to test -march=riscv which
> > > > is not a value value.
> > > >
> > > > The generic setting used in most cases is rv64gc, set this here
> > > > as well.
> > > >
> > > > Fixes: b7676fcccab4 ("config: verify machine arch flag")
> > > > Fixes: f22e705ebf12 ("eal/riscv: support RISC-V architecture")
> > > >
> > > > Signed-off-by: Christian Ehrhardt <christian.ehrhardt@canonical.com>
> > > > ---
> > > > config/meson.build | 2 +-
> > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/config/meson.build b/config/meson.build
> > > > index d732154731..a9ccd56deb 100644
> > > > --- a/config/meson.build
> > > > +++ b/config/meson.build
> > > > @@ -152,7 +152,7 @@ if cpu_instruction_set == 'generic'
> > > > elif host_machine.cpu_family().startswith('ppc')
> > > > cpu_instruction_set = 'power8'
> > > > elif host_machine.cpu_family().startswith('riscv')
> > > > - cpu_instruction_set = 'riscv'
> > > > + cpu_instruction_set = 'rv64gc'
> > >
> > > Copying more people.
> > >
> > > This fix is probably the best, so close to the release.
> > >
> >
> > Agreed
>
> I took this patch as is, for now.
Sorry for reviving an old thread, I was on a rather long OoO, hence I
did not answer.
Thank you for taking this patch.
>
> >
> > >
> > > However, I think a more complete fix would be to set this here to generic.
> > > And do the march validation in config/riscv/meson.build in a similar
> > > fashion to ARM.
> > >
> > > Or maybe the validation added in b7676fcccab4 ("config: verify machine
> > > arch flag") should be moved after subdir(arch_subdir).
> > > Bruce, opinion?
> > >
> >
> > Probably the first of these two is best, to do the march validation in the
> > riscv-specific file. However, I've no strong opinions either way.
>
> Stanislaw, could you look at doing some enhancement on this topic?
> And, in any case, what we lack is a CI for RISC V.
It seems that there is not much traction for RISC-V DPDK yet. StarFive
seems to be focused more on the platform side of things and therefore
I don't have any server-grade HW to really run CI on.
>
>
> --
> David Marchand
>
--
Best Regards,
Stanisław Kardach
next prev parent reply other threads:[~2024-01-05 15:51 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-21 16:49 christian.ehrhardt
2023-11-22 13:27 ` Tummala, Sivaprasad
2023-11-22 16:02 ` David Marchand
2023-11-22 16:17 ` Bruce Richardson
2023-11-22 16:41 ` David Marchand
2024-01-05 15:50 ` Stanisław Kardach [this message]
2023-11-22 16:39 ` David Marchand
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