From: "Stanisław Kardach" <kda@semihalf.com>
To: Stephen Hemminger <stephen@networkplumber.org>
Cc: dev <dev@dpdk.org>, Frank Zhao <Frank.Zhao@starfivetech.com>,
Sam Grove <sam.grove@sifive.com>,
Marcin Wojtas <mw@semihalf.com>,
upstream@semihalf.com, pbhagavatula@marvell.com
Subject: Re: [PATCH 02/11] examples/l3fwd: fix scalar LPM compilation
Date: Thu, 5 May 2022 19:49:28 +0200 [thread overview]
Message-ID: <CALVGJWLfKFqDr_MROJ==oyvBMV-PVf8esrbZBBEaToHmcRdunQ@mail.gmail.com> (raw)
In-Reply-To: <20220505103951.2c58b9d0@hermes.local>
[-- Attachment #1: Type: text/plain, Size: 1832 bytes --]
On Thu, May 5, 2022 at 7:39 PM Stephen Hemminger <stephen@networkplumber.org>
wrote:
> On Thu, 5 May 2022 19:29:54 +0200
> Stanislaw Kardach <kda@semihalf.com> wrote:
>
> > The lpm_process_event_pkt() can either process a packet using an
> > architecture specific (defined for X86/SSE, ARM/Neon and PPC64/Altivec)
> > path or a scalar one. The choice is however done using an ifdef
> > pre-processor macro. Because of that the scalar version was apparently
> > not widely excersized/compiled.
> > Due to some copy/paste errors, the scalar logic in
> > lpm_process_event_pkt() retained a "continue" statement where a BAD_PORT
> > should be returned after refactoring of the LPM logic in the l3fwd
> > example.
> >
> > Fixes: 99fc91d18082 ("examples/l3fwd: add event lpm main loop")
> > Cc: pbhagavatula@marvell.com
> >
> > Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
> > Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
> > Sponsored-by: Sam Grove <sam.grove@sifive.com>
>
> Would be easier to get merged if bug fixes came as separate patch
> submission.
>
Sure, I can post this separately. The reason for posting this along with
RISC-V patches is that those depend on this one. So I could add
"depends-on" but wanted be on the safe side.
>
> Also have not seen Sponsored-by before; what do you expect it to mean?
> Never used in DPDK or kernel git tree.
>
The idea is that this work was sponsored by the companies mentioned in the
sign-off. It is used i.e. in FreeBSD though admittedly never in Linux or
DPDK.
Alternative, which makes checkpatch happy and was previously used is
"Suggested-by". However suggestion, doesn't necessary mean sponsorship.
I had a talk about this with Thomas Monjalon and he has also leaned towards
"Sponsored-by".
I'm open to suggestions as I admit, I'm not sure which route is better.
[-- Attachment #2: Type: text/html, Size: 2782 bytes --]
next prev parent reply other threads:[~2022-05-05 17:50 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-05 17:29 [PATCH 00/11] Introduce support for RISC-V architecture Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 01/11] lpm: add a scalar version of lookupx4 function Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 02/11] examples/l3fwd: fix scalar LPM compilation Stanislaw Kardach
2022-05-05 17:39 ` Stephen Hemminger
2022-05-05 17:49 ` Stanisław Kardach [this message]
2022-05-05 18:09 ` Stephen Hemminger
2022-05-05 17:29 ` [PATCH 03/11] eal: add initial support for RISC-V architecture Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 04/11] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 05/11] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 06/11] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 07/11] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 08/11] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 09/11] test/ring: disable problematic tests for RISC-V Stanislaw Kardach
2022-05-05 17:35 ` Stephen Hemminger
2022-05-05 17:43 ` Stanisław Kardach
2022-05-05 18:06 ` Stephen Hemminger
2022-05-10 23:28 ` Honnappa Nagarahalli
2022-05-11 10:07 ` Stanisław Kardach
2022-05-05 17:30 ` [PATCH 10/11] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 11/11] test/hash: report non HTM numbers for single r/w Stanislaw Kardach
2022-05-06 9:13 ` [PATCH 00/11] Introduce support for RISC-V architecture David Marchand
2022-05-09 12:24 ` Stanisław Kardach
2022-05-09 12:30 ` Thomas Monjalon
2022-05-11 8:09 ` Morten Brørup
2022-05-11 10:28 ` Stanisław Kardach
2022-05-11 11:06 ` Thomas Monjalon
2022-05-09 14:30 ` David Marchand
2022-05-10 11:21 ` Stanisław Kardach
2022-05-10 12:31 ` Thomas Monjalon
2022-05-10 14:00 ` Stanisław Kardach
2022-05-10 14:23 ` Thomas Monjalon
2022-05-10 15:07 ` [PATCH v2 0/8] " Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 1/8] eal: add initial " Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 2/8] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 3/8] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 4/8] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 5/8] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 6/8] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 7/8] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-10 15:35 ` Stanisław Kardach
2022-05-10 15:07 ` [PATCH v2 8/8] ci: add RISCV64 cross compilation job Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 0/8] Introduce support for RISC-V architecture Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 1/8] eal: add initial " Stanislaw Kardach
2022-05-13 6:50 ` Heinrich Schuchardt
2022-05-13 8:42 ` Stanisław Kardach
2022-05-13 10:51 ` Heinrich Schuchardt
2022-05-13 11:47 ` Stanisław Kardach
2022-05-13 15:37 ` Stephen Hemminger
2022-05-16 8:00 ` Stanisław Kardach
2022-05-10 15:48 ` [PATCH v3 2/8] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 3/8] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 4/8] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 5/8] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 6/8] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 7/8] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 8/8] ci: add RISCV64 cross compilation job Stanislaw Kardach
2022-05-12 15:47 ` Aaron Conole
2022-05-12 16:07 ` Stanisław Kardach
2022-05-13 14:33 ` Aaron Conole
2022-05-12 8:04 ` [PATCH 00/11] Introduce support for RISC-V architecture Heinrich Schuchardt
2022-05-12 8:35 ` Stanisław Kardach
2022-05-12 9:46 ` Heinrich Schuchardt
2022-05-12 13:56 ` Stanisław Kardach
2022-05-12 21:06 ` Heinrich Schuchardt
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CALVGJWLfKFqDr_MROJ==oyvBMV-PVf8esrbZBBEaToHmcRdunQ@mail.gmail.com' \
--to=kda@semihalf.com \
--cc=Frank.Zhao@starfivetech.com \
--cc=dev@dpdk.org \
--cc=mw@semihalf.com \
--cc=pbhagavatula@marvell.com \
--cc=sam.grove@sifive.com \
--cc=stephen@networkplumber.org \
--cc=upstream@semihalf.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).