> is just a reminder if it is useful.
Our deployment needs to balance the DPDK release, our FPGA firmware, our (not yet
published) DPDKpatches and external FPGA-IP firmware from AMD (Xilinx) and Intel
(Altera). We have safety code to ensure that these fall into a valid alignment. We also
try to maintain SW/FPGA compatibility and evolve without breaking things unnecessarily.
Our releases follow DPDK's and we update other tools as they are released.
For RQ pacing, it was an internal feature needed for older Xilinx PCIE IP, with a
narrow exposure via our PMD. The Xilinx IP no longer requires this module, our
firmware no longer includes it, and the PMD can drop. It was not user controllable
nor an advertised feature.
>This change is in error. Thanks for catching it. New patch to follow.