From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0A2264234D; Tue, 10 Oct 2023 16:50:52 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 76B3740A6F; Tue, 10 Oct 2023 16:50:47 +0200 (CEST) Received: from mail-lj1-f171.google.com (mail-lj1-f171.google.com [209.85.208.171]) by mails.dpdk.org (Postfix) with ESMTP id 1D51740297 for ; Tue, 10 Oct 2023 16:50:45 +0200 (CEST) Received: by mail-lj1-f171.google.com with SMTP id 38308e7fff4ca-2c131ddfeb8so66581211fa.3 for ; Tue, 10 Oct 2023 07:50:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=atomicrules-com.20230601.gappssmtp.com; s=20230601; t=1696949444; x=1697554244; darn=dpdk.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=OfwAmf930Kna3NVETUVcXy2/DAAAlitrkIuil5UFMBk=; b=s9PzVJ9iDmciqjo05p1i9luuDuEafOTVQFp0+mvl/LHqP2k1GIqq74TFCrlyRFNd24 kAxq0C6wEZjfJFZzgNOle3fBay52hB+N9RHPToaQoI+sJSH/p2cjCuR6RASJcVhIXgBF daAS/yZ9Bq1WfIVJZBrWXMs7vpiyhXvF9plSsH988LovoVvQIwi0A2g+oYdJF7jSgV35 A6KDFzE628Cx/JMQLApakY40bycVbFWdoi1RbAsG62VtjtA9vjB9rNxZ+hirNFGKEj9e pP51U2xoF0zMKOdBtq38sEufgp157DF80K4S8OhL69YWVvuaxNlsAOByoTzknsmw2IOF G+Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696949444; x=1697554244; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=OfwAmf930Kna3NVETUVcXy2/DAAAlitrkIuil5UFMBk=; b=UOwLEpzQr0IcaSgkJQ6e8rxMcpllu1SNPhynZrI9MaCoMZnkOyZdESuVxph3IJbJ39 QjFII0VOmMjttgQy47YbXKGrkY1GfSITzmRXrvCataYTxov4CwYFlG4lp77Pa75HBZyD /7pesJ/5tygmXPEnVRL391UH11ZiQeE2u5NEvqCNddtUp2SasVN3SL2pxC6qIyGmdxVn iCOcqLelnIK00rDPyfBBxoteSfzGKljgd8ACEDlpBpp73RnQ6UmAAg7djxbiBVn3ZT7l IeLb6qtc7JPLeuw6KkA5g/gWIknHRSkmTFZN23UuWFMeYivVO4MD8RtWH3wklvWcRGtS k2bw== X-Gm-Message-State: AOJu0YyAApJEFivK1rAhTN7tKKp8R71mT835wuQBkg5VzEtDcCaoxVxu vVqJVl/7FZzyw/U3J+rs8vbN8NvvK9ELN8DrpPEIOw== X-Google-Smtp-Source: AGHT+IG84d4NXbWbXUxH31ePSnrc9rD1cIddOYokQ0n6xIrraVL31O293SDtrxe8KuHTgyTru4nvF8pgpbZyDiVU+to= X-Received: by 2002:a05:651c:91:b0:2c0:fa5:8e0e with SMTP id 17-20020a05651c009100b002c00fa58e0emr14439272ljq.40.1696949444385; Tue, 10 Oct 2023 07:50:44 -0700 (PDT) MIME-Version: 1.0 References: <20231005205217.1753187-1-ed.czeck@atomicrules.com> <20231005205217.1753187-2-ed.czeck@atomicrules.com> <59b9f084-1743-41ba-86ea-82ad02b2c66f@amd.com> In-Reply-To: <59b9f084-1743-41ba-86ea-82ad02b2c66f@amd.com> From: Ed Czeck Date: Tue, 10 Oct 2023 10:50:33 -0400 Message-ID: Subject: Re: [PATCH 2/3] net/ark: remove RQ pacing firmware from PMD To: Ferruh Yigit Cc: dev@dpdk.org, Shepard Siegel , John Miller Content-Type: multipart/alternative; boundary="000000000000d5b46606075dd422" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org --000000000000d5b46606075dd422 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Oct 10, 2023 at 9:51=E2=80=AFAM Ferruh Yigit = wrote: > > On 10/5/2023 9:52 PM, Ed Czeck wrote: > > features and function have been removed from FPGA firmware > > > > I am always a little confused how you manage the deployment, if a > customer requires RQ pacing, how you manage it, at least should it be > documented in driver documentation that RQ pacing supported before > v23.11, or something like that? > If this doesn't make sense for your deployment model, scratch it, this > is just a reminder if it is useful. Our deployment needs to balance the DPDK release, our FPGA firmware, our (not yet published) DPDKpatches and external FPGA-IP firmware from AMD (Xilinx) and Intel (Altera). We have safety code to ensure that these fall into a valid alignment. We also try to maintain SW/FPGA compatibility and evolve without breaking things unnecessarily. Our releases follow DPDK's and we update other tools as they are released. For RQ pacing, it was an internal feature needed for older Xilinx PCIE IP, with a narrow exposure via our PMD. The Xilinx IP no longer requires this module, our firmware no longer includes it, and the PMD can drop. It was not user controllable nor an advertised feature. > > > > Signed-off-by: Ed Czeck > > --- > > drivers/net/ark/ark_ethdev.c | 62 ++++++++------------------------ > > drivers/net/ark/ark_global.h | 3 -- > > drivers/net/ark/ark_rqp.c | 70 ------------------------------------ > > drivers/net/ark/ark_rqp.h | 58 ------------------------------ > > drivers/net/ark/meson.build | 1 - > > 5 files changed, 15 insertions(+), 179 deletions(-) > > delete mode 100644 drivers/net/ark/ark_rqp.c > > delete mode 100644 drivers/net/ark/ark_rqp.h > > > > diff --git a/drivers/net/ark/ark_ethdev.c b/drivers/net/ark/ark_ethdev.= c > > index 90d3c8abe6..306121ba31 100644 > > --- a/drivers/net/ark/ark_ethdev.c > > +++ b/drivers/net/ark/ark_ethdev.c > > @@ -17,7 +17,6 @@ > > #include "ark_mpu.h" > > #include "ark_ddm.h" > > #include "ark_udm.h" > > -#include "ark_rqp.h" > > #include "ark_pktdir.h" > > #include "ark_pktgen.h" > > #include "ark_pktchkr.h" > > @@ -107,36 +106,32 @@ static const struct rte_pci_id pci_id_ark_map[] = =3D { > > * This structure is used to statically define the capabilities > > * of supported devices. > > * Capabilities: > > - * rqpacing - > > - * Some HW variants require that PCIe read-requests be correctly throttled. > > - * This is called "rqpacing" and has to do with credit and flow contro= l > > - * on certain Arkville implementations. > > + * isvf -- defined for function id that are virtual > > */ > > struct ark_caps { > > - bool rqpacing; > > bool isvf; > > }; > > struct ark_dev_caps { > > uint32_t device_id; > > struct ark_caps caps; > > }; > > -#define SET_DEV_CAPS(id, rqp, vf) \ > > - {id, {.rqpacing =3D rqp, .isvf =3D vf} } > > +#define SET_DEV_CAPS(id, vf) \ > > + {id, {.isvf =3D vf} } > > > > static const struct ark_dev_caps > > ark_device_caps[] =3D { > > - SET_DEV_CAPS(0x100d, true, false), > > - SET_DEV_CAPS(0x100e, true, false), > > - SET_DEV_CAPS(0x100f, true, false), > > - SET_DEV_CAPS(0x1010, false, false), > > - SET_DEV_CAPS(0x1017, true, false), > > - SET_DEV_CAPS(0x1018, true, false), > > - SET_DEV_CAPS(0x1019, true, false), > > - SET_DEV_CAPS(0x101a, true, false), > > - SET_DEV_CAPS(0x101b, true, false), > > - SET_DEV_CAPS(0x101c, true, true), > > - SET_DEV_CAPS(0x101e, false, false), > > - SET_DEV_CAPS(0x101f, false, false), > > + SET_DEV_CAPS(0x100d, false), > > + SET_DEV_CAPS(0x100e, false), > > + SET_DEV_CAPS(0x100f, false), > > + SET_DEV_CAPS(0x1010, false), > > + SET_DEV_CAPS(0x1017, false), > > + SET_DEV_CAPS(0x1018, false), > > + SET_DEV_CAPS(0x1019, false), > > + SET_DEV_CAPS(0x101a, false), > > + SET_DEV_CAPS(0x101b, false), > > + SET_DEV_CAPS(0x101c, true), > > + SET_DEV_CAPS(0x101e, false), > > + SET_DEV_CAPS(0x101f, false), > > {.device_id =3D 0,} > > }; > > > > @@ -301,9 +296,6 @@ eth_ark_dev_init(struct rte_eth_dev *dev) > > int port_count =3D 1; > > int p; > > uint16_t num_queues; > > - bool rqpacing =3D false; > > - > > - ark->eth_dev =3D dev; > > > > Above "ark->eth_dev" assignment doesn't look directly related with RQ > pacing, I just want to double check if it is removed intentionally? This change is in error. Thanks for catching it. New patch to follow. > > --000000000000d5b46606075dd422 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Tue, Oct 10, 2023 at 9:51=E2=80=AFAM Ferruh Yig= it <ferruh.yigit@amd.com>= wrote:
>
> On 10/5/2023 9:52 PM, Ed Czeck wrote:
> > = features and function have been removed from FPGA firmware
> >
= >
> I am always a little confused how you manage the deployment, i= f a
> customer requires RQ pacing, how you manage it, at least should= it be
> documented in driver documentation that RQ pacing supported = before
> v23.11, or something like that?
> If this doesn't = make sense for your deployment model, scratch it, this
> is just= a reminder if it is useful.

Our deployment n= eeds to balance the DPDK =C2=A0release, our FPGA firmware, our (not yet
published) DPDKpatches and external FPGA-IP firmware from AMD (Xilin= x) and Intel=C2=A0
(Altera).=C2=A0 We have safety code to ensure = that these fall into a valid alignment. We also=C2=A0
try to main= tain SW/FPGA compatibility and evolve without breaking things unnecessarily= .=C2=A0
Our releases follow DPDK's and we update other tools = as they are released.

For RQ pacing, it was an internal featu= re needed for older Xilinx PCIE IP, with a
narrow exposure via ou= r PMD.=C2=A0 The Xilinx IP no longer requires this module, our
fi= rmware no longer includes it, and the PMD can drop.=C2=A0 It was not user c= ontrollable=C2=A0
nor an advertised feature.

>
>
> > Signed-off-by: Ed Czeck <ed.czeck@atomicrules.com>
> &= gt; ---
> > =C2=A0drivers/net/ark/ark_ethdev.c | 62 ++++++++------= ------------------
> > =C2=A0drivers/net/ark/ark_global.h | =C2=A0= 3 --
> > =C2=A0drivers/net/ark/ark_rqp.c =C2=A0 =C2=A0| 70 -------= -----------------------------
> > =C2=A0drivers/net/ark/ark_rqp.h = =C2=A0 =C2=A0| 58 ------------------------------
> > =C2=A0drivers= /net/ark/meson.build =C2=A0| =C2=A01 -
> > =C2=A05 files changed, = 15 insertions(+), 179 deletions(-)
> > =C2=A0delete mode 100644 dr= ivers/net/ark/ark_rqp.c
> > =C2=A0delete mode 100644 drivers/net/a= rk/ark_rqp.h
> >
> > diff --git a/drivers/net/ark/ark_eth= dev.c b/drivers/net/ark/ark_ethdev.c
> > index 90d3c8abe6..306121b= a31 100644
> > --- a/drivers/net/ark/ark_ethdev.c
> > +++= b/drivers/net/ark/ark_ethdev.c
> > @@ -17,7 +17,6 @@
> >= =C2=A0#include "ark_mpu.h"
> > =C2=A0#include "ark= _ddm.h"
> > =C2=A0#include "ark_udm.h"
> >= -#include "ark_rqp.h"
> > =C2=A0#include "ark_pktd= ir.h"
> > =C2=A0#include "ark_pktgen.h"
> >= ; =C2=A0#include "ark_pktchkr.h"
> > @@ -107,36 +106,32 = @@ static const struct rte_pci_id pci_id_ark_map[] =3D {
> > =C2= =A0 * This structure is used to statically define the capabilities
> = > =C2=A0 * of supported devices.
> > =C2=A0 * Capabilities:
= > > - * =C2=A0rqpacing -
> > - * Some HW variants require th= at PCIe read-requests be correctly throttled.
> > - * This is call= ed "rqpacing" and has to do with credit and flow control
> = > - * on certain Arkville implementations.
> > + * =C2=A0 =C2= =A0isvf -- defined for function id that are virtual
> > =C2=A0 */<= br>> > =C2=A0struct ark_caps {
> > - =C2=A0 =C2=A0 bool rqpa= cing;
> > =C2=A0 =C2=A0 =C2=A0 bool isvf;
> > =C2=A0};> > =C2=A0struct ark_dev_caps {
> > =C2=A0 =C2=A0 =C2=A0 ui= nt32_t =C2=A0device_id;
> > =C2=A0 =C2=A0 =C2=A0 struct ark_caps = =C2=A0caps;
> > =C2=A0};
> > -#define SET_DEV_CAPS(id, rq= p, vf) =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0\
> > - =C2=A0 =C2=A0 {id, {.rqpacing =3D rqp, .isvf =3D vf} }<= br>> > +#define SET_DEV_CAPS(id, vf) =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 \
> > + =C2=A0 =C2=A0 {id, {.isvf =3D vf}= }
> >
> > =C2=A0static const struct ark_dev_caps
>= > =C2=A0ark_device_caps[] =3D {
> > - =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SET_DEV_CAPS(0x100d, true, false),> > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= SET_DEV_CAPS(0x100e, true, false),
> > - =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SET_DEV_CAPS(0x100f, true, false),> > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= SET_DEV_CAPS(0x1010, false, false),
> > - =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SET_DEV_CAPS(0x1017, true, false),> > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= SET_DEV_CAPS(0x1018, true, false),
> > - =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SET_DEV_CAPS(0x1019, true, false),> > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= SET_DEV_CAPS(0x101a, true, false),
> > - =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SET_DEV_CAPS(0x101b, true, false),> > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= SET_DEV_CAPS(0x101c, true, true),
> > - =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SET_DEV_CAPS(0x101e, false, false),> > - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0SET_DEV_CAPS(0x101f, false, false),
> > + =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SET_DEV_CAPS(0x100d, false),
&g= t; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SET= _DEV_CAPS(0x100e, false),
> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0SET_DEV_CAPS(0x100f, false),
> > + =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SET_DEV_CAPS(0x1= 010, false),
> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0SET_DEV_CAPS(0x1017, false),
> > + =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SET_DEV_CAPS(0x1018, false)= ,
> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0SET_DEV_CAPS(0x1019, false),
> > + =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SET_DEV_CAPS(0x101a, false),
> = > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SET_DE= V_CAPS(0x101b, false),
> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0SET_DEV_CAPS(0x101c, true),
> > + =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SET_DEV_CAPS(0x1= 01e, false),
> > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0SET_DEV_CAPS(0x101f, false),
> > =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0{.device_id =3D 0,}<= br>> > =C2=A0};
> >
> > @@ -301,9 +296,6 @@ eth_ark= _dev_init(struct rte_eth_dev *dev)
> > =C2=A0 =C2=A0 =C2=A0 int po= rt_count =3D 1;
> > =C2=A0 =C2=A0 =C2=A0 int p;
> > =C2= =A0 =C2=A0 =C2=A0 uint16_t num_queues;
> > - =C2=A0 =C2=A0 bool rq= pacing =3D false;
> > -
> > - =C2=A0 =C2=A0 ark->eth_d= ev =3D dev;
> >
>
> Above "ark->eth_dev" = assignment doesn't look directly related with RQ
> pacing, I= just want to double check if it is removed intentionally?

This change is in error.=C2=A0=C2=A0 Thanks for catching it.=C2=A0= New patch to follow.

>
>
--000000000000d5b46606075dd422--