From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wg0-f50.google.com (mail-wg0-f50.google.com [74.125.82.50]) by dpdk.org (Postfix) with ESMTP id 98A65683D for ; Wed, 1 Jul 2015 15:05:11 +0200 (CEST) Received: by wguu7 with SMTP id u7so36280466wgu.3 for ; Wed, 01 Jul 2015 06:05:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=u2KV0dyZcI8YvzxC9FVTamXvuJxJjI9Zo661Hw5Uhzg=; b=hk+CB3wM6E5EnFVytaaLwb4kZCVaWxAsg7ncECWOWia+nqCWr4fJ41zI5JTh9TRSxX PwY2MFUpFOPGre41RP4lTLUC2wDAHqm8txKaX2724x9KpiIRe4nlXXxfD3oCJs4mEop8 p9fznaIhArQXxEah/v1MOh3AOwGm3sTfEGAivmCDRguAhLY1a29U7lM32RYFVZXPS9nO kammjeOhYP1oTbItdb89Tg6fdEk0GlBVEkCIvUl6EVEawVgAXpaS1uRi8Ik0JpyFQH9V cjI41jRc0cV9Sw78nvIgQcuoW0jv1WwrHCrwGzcvLtKuy8gjBVxqN2jZpE5NcjQq5iUC MABg== MIME-Version: 1.0 X-Received: by 10.180.206.33 with SMTP id ll1mr43679820wic.91.1435755911505; Wed, 01 Jul 2015 06:05:11 -0700 (PDT) Received: by 10.27.178.129 with HTTP; Wed, 1 Jul 2015 06:05:11 -0700 (PDT) In-Reply-To: <20150701125918.GA6960@bricha3-MOBL3> References: <20150701125918.GA6960@bricha3-MOBL3> Date: Wed, 1 Jul 2015 16:05:11 +0300 Message-ID: From: Pavel Odintsov To: Bruce Richardson Content-Type: text/plain; charset=UTF-8 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] Could not achieve wire speed for 40GE with any DPDK version on XL710 NIC's X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Jul 2015 13:05:11 -0000 Yes, Bruce, we understand this. But we are working with huge SYN attacks processing and they are 64byte only :( On Wed, Jul 1, 2015 at 3:59 PM, Bruce Richardson wrote: > On Wed, Jul 01, 2015 at 03:44:57PM +0300, Pavel Odintsov wrote: >> Thanks for answer, Vladimir! So we need look for x16 NIC if we want >> achieve 40GE line rate... >> > Note that this would only apply for your minimal i.e. 64-byte, packet sizes. > Once you go up to larger e.g. 128B packets, your PCI bandwidth requirements > are lower and you can easier achieve line rate. > > /Bruce > >> On Wed, Jul 1, 2015 at 3:06 PM, Vladimir Medvedkin wrote: >> > Hi Pavel, >> > >> > Looks like you ran into pcie bottleneck. So let's calculate xl710 rx only >> > case. >> > Assume we have 32byte descriptors (if we want more offload). >> > DMA makes one pcie transaction with packet payload, one descriptor writeback >> > and one memory request for free descriptors for every 4 packets. For >> > Transaction Layer Packet (TLP) there is 30 bytes overhead (4 PHY + 6 DLL + >> > 16 header + 4 ECRC). So for 1 rx packet dma sends 30 + 64(packet itself) + >> > 30 + 32 (writeback descriptor) + (16 / 4) (read request for new >> > descriptors). Note that we do not take into account PCIe ACK/NACK/FC Update >> > DLLP. So we have 160 bytes per packet. One lane PCIe 3.0 transmits 1 byte in >> > 1 ns, so x8 transmits 8 bytes in 1 ns. 1 packet transmits in 20 ns. Thus >> > in theory pcie 3.0 x8 may transfer not more than 50mpps. >> > Correct me if I'm wrong. >> > >> > Regards, >> > Vladimir >> > >> > -- Sincerely yours, Pavel Odintsov