From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi0-f51.google.com (mail-oi0-f51.google.com [209.85.218.51]) by dpdk.org (Postfix) with ESMTP id 7A6EFB3A0 for ; Wed, 17 Sep 2014 15:57:25 +0200 (CEST) Received: by mail-oi0-f51.google.com with SMTP id x69so929824oia.38 for ; Wed, 17 Sep 2014 07:03:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=qVMxMMsx/I4/+++t8+uC7xXVMCAeMpSm2fkx0UPo8xI=; b=NuQ1f6zTtl30keOI40eu9KU6tAfjl1LGMbe0Y4KOKRqGNKyFkMbbxt3kHnh21Ok0YU jsYmse/F19Q0ixXOPWEgGOwCIf7xR9tTa0faKDImuN03+jc96bmUM7dqSTw5GseNDodO JnDrwQG55ifmqAXjCFql65RJNRaZMgiwrYKisx8ItuBuqLDKqXWRnfzNfpxE0JB6ox3s 8/Wu5lzfrKtkrUmmrr9zqiF4UgBCF8In7uU5oBMwRgygnBaqHLCLxCOs0wLMEPTEqh4s gY01FEGzJdMfOILTkQ7/F0J7Ku8YHkMm5bJWX/fC2g+ukKMD87S0/cTuwC2trcwuHhi7 SWCQ== X-Gm-Message-State: ALoCoQnE3kJPTBIBRysMIHd8va+3D2gMnDJmmcmGSDWL3WzE9iSaCmgh1CV2pIMeJaRg9chjzzla MIME-Version: 1.0 X-Received: by 10.182.119.230 with SMTP id kx6mr18683727obb.72.1410962585405; Wed, 17 Sep 2014 07:03:05 -0700 (PDT) Received: by 10.202.13.21 with HTTP; Wed, 17 Sep 2014 07:03:05 -0700 (PDT) In-Reply-To: References: Date: Wed, 17 Sep 2014 16:03:05 +0200 Message-ID: From: David Marchand To: "Zhang, Helin" Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] i40e: Steps and required configurations of how to achieve the best performance! X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 17 Sep 2014 13:57:26 -0000 On Wed, Sep 17, 2014 at 10:50 AM, Zhang, Helin wrote: > For the =E2=80=98extended tag=E2=80=99, it was defined in PCIe spec, but= actually not > all BIOS implements it. Enabling it in BIOS or at runtime are two choices > of doing the same thing. I don=E2=80=99t think it can be configured per P= CI device > in BIOS, so we don=E2=80=99t need to do that per PCI device in DPDK. Righ= t? > Actually we don=E2=80=99t want to touch PCIe settings in DPDK code, that= =E2=80=99s why we > want to let BIOS config as it is by default. If no better choice, we can = do > it in DPDK by changing configurations. > - Ok, then if we can make a runtime decision (at dpdk level), there is no need for bios configuration and there is no need for a build option. Why don't we get rid of this option ? As far as the per-device runtime configuration is concerned, I want to make sure this pci configuration will not break other "igb_uio" pci devices. If Intel can tell for sure this won't break other devices, then fine, we can go and enable this for all "igb_uio" pci devices. - By the way, there is also the CONFIG_MAX_READ_REQUEST_SIZE option that seems to be disabled (or at least its value 0 seems to tell so). What is its purpose ? > > For =E2=80=98CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=3Dn=E2=80=99 by defaul= t, we want to > support 32 bytes rx descriptors by default. Two reasons: > > One is 32 bytes rx descriptors can provide more powerful features, and > more offload features. > > The other is Linux PF host use 32 bytes rx descriptor by default which > might not able to be changed, to support Linux PF host, it would be bette= r > to use 32 bytes rx descriptors in DPDK VF by default. > Ok, good to know. Thanks. --=20 David Marchand