From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f41.google.com (mail-wm0-f41.google.com [74.125.82.41]) by dpdk.org (Postfix) with ESMTP id 25246960D for ; Fri, 13 May 2016 16:28:47 +0200 (CEST) Received: by mail-wm0-f41.google.com with SMTP id a17so33314812wme.0 for ; Fri, 13 May 2016 07:28:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=bmoPtonsjEbXgNTDHB1P5xn2SsRemyJY0Jl8ikfCtCI=; b=IZzCpu7of8JGctjzLvChCy1wC6mCm7TxOUsbOJxaOrOXL9fV30YlDucuEQleG5LzfR oN86z/qQ+eo1soRw0N1ROYND0NElMYmi7DMZDTGTcmmd3HQMiXInUqepafPv3WGkBXsU 8IMO8Ns9F2NhO9diUdiUg/AOEMU+Vnb9eOOy2pSXV4hLUnMNm7H18WL4f4XjVGbcdK3h YfJ1mZjkhaNfGpL1rwh+XsW4GvgjkHJ5u4AArucQxzJp2AXu0alkw4Mibj0OtZLTINrA OJCTxQLBCuik0/bcBBLbjPpwFYaar8iYv73R1Rs8jSAUJSqDE0YiwtYYmH6U94U0fb9u tnVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=bmoPtonsjEbXgNTDHB1P5xn2SsRemyJY0Jl8ikfCtCI=; b=JzSaxQvgE5+RR58CeZUIlHQ7vSnPlAw7OsEfkUxwKB6cYJ9UWuq3b251G/MGk3vFz3 K26sb++nZkQjAi8XFQUFc3FLtjOQQPcgekL+XfH3vTEfl03GTPvV9iZjnfIHy0XRmt1/ oZ/c2TAZahSE7nhwsCWYTyxdehdy8AdsbcbXDdqhNuqAUuFjHy224esQAfaLWT42Eg7+ juDNuqEs2R9juHqAUTRSzWUG1n0okPb/90tyHCJQQXhiK2IqlzaxCQb3PDouGqndEsqB buz/FmMc29oUXoJdoR5KJ/YsAWs7TeXDGhYrZkcZgwDlLI7tVdYet5SLThAkwCZoCZzu 9ahw== X-Gm-Message-State: AOPr4FXMVDluo7kvsQsb44ljn0BrYJuN1hMR9r6F6HB0kL30B5e4ytUgRcv5cmrLUdywTdAplKqFJRVsKxvMhuk+ X-Received: by 10.28.236.88 with SMTP id k85mr4156033wmh.53.1463149726816; Fri, 13 May 2016 07:28:46 -0700 (PDT) MIME-Version: 1.0 Received: by 10.28.16.2 with HTTP; Fri, 13 May 2016 07:28:27 -0700 (PDT) In-Reply-To: <1463143859-3105-7-git-send-email-olivier.matz@6wind.com> References: <1463143859-3105-1-git-send-email-olivier.matz@6wind.com> <1463143859-3105-7-git-send-email-olivier.matz@6wind.com> From: David Marchand Date: Fri, 13 May 2016 16:28:27 +0200 Message-ID: To: Olivier Matz Cc: "dev@dpdk.org" , Chao Zhu Content-Type: text/plain; charset=UTF-8 Subject: Re: [dpdk-dev] [PATCH 6/7] virtio: fix pci accesses for ppc64 in legacy mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 May 2016 14:28:47 -0000 Hello Olivier, On Fri, May 13, 2016 at 2:50 PM, Olivier Matz wrote: > From: David Marchand > > Although ppc supports both endianesses, qemu supposes that the cpu is > big endian and enforces this for the virtio-net stuff. > > Fix PCI accesses in legacy mode. Only ppc64le is supported at the moment. > > Signed-off-by: David Marchand > Signed-off-by: Olivier Matz > --- > drivers/net/virtio/virtio_pci.c | 44 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c > index 9cdca06..bdb89fd 100644 > --- a/drivers/net/virtio/virtio_pci.c > +++ b/drivers/net/virtio/virtio_pci.c > @@ -55,18 +55,62 @@ > */ > #define VIRTIO_PCI_CONFIG(hw) (((hw)->use_msix) ? 24 : 20) > > +/* > + * Since we are in legacy mode: > + * http://ozlabs.org/~rusty/virtio-spec/virtio-0.9.5.pdf > + * > + * "Note that this is possible because while the virtio header is PCI (i.e. > + * little) endian, the device-specific region is encoded in the native endian of > + * the guest (where such distinction is applicable)." > + * > + * For powerpc which supports both, qemu supposes that cpu is big endian and > + * enforces this for the virtio-net stuff. > + */ > + > static void > legacy_read_dev_config(struct virtio_hw *hw, size_t offset, > void *dst, int length) > { > rte_eal_pci_ioport_read(&hw->io, dst, length, > VIRTIO_PCI_CONFIG(hw) + offset); > +#ifdef RTE_ARCH_PPC_64 > + switch (length) { > + case 4: > + *(uint32_t *)dst = rte_be_to_cpu_32(*(uint32_t *)dst); > + break; > + case 2: > + *(uint16_t *)dst = rte_be_to_cpu_16(*(uint16_t *)dst); > + break; > + default: > + break; > + } > +#endif > } I think that, in the original patch, I was handling lengths different than 1, 2 and 4 ;-) Idem for write. -- David Marchand