From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa0-f44.google.com (mail-oa0-f44.google.com [209.85.219.44]) by dpdk.org (Postfix) with ESMTP id 3EB61B3A3 for ; Thu, 18 Sep 2014 10:52:04 +0200 (CEST) Received: by mail-oa0-f44.google.com with SMTP id eb12so428753oac.31 for ; Thu, 18 Sep 2014 01:57:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=F1GqfensssZZy1AUv3TBj0tSH3YEICwRSc9337oLV70=; b=PKjK73ADL16x+LITNXxGVBejhmJfRvJyu4WGRrBq4T88zlh/2FClu/K9PA093TF4ZY laJ8f/S56Dj41T4dJHrzIxj6J2WfPeVY/GNnBhiKXK7DxFsAqQMwQ77bW6tWHxLlzBPd DSCikSdkU7ed1+5FAabsTuScSK31N6zh/hs19O8ms+sOh69Y7p0RGW9QilMKxxoFCT8p UNSNX275gj0QB/JbtOIKC9QUI545D6+yFYSIZwei7gcgWBlPYoogM/EEburkStFcJ/ND K8TpY2us2Pb+yo6Ovj8E2/thF4yI/8kyim6PjSXokwCEZs0EqqetpiMtrKYMZLpjKt8j LROA== X-Gm-Message-State: ALoCoQlAZHLQyFIAOT37AwEjsJJoATmTxYcBJb47vrK1VOyLZvRS2z+gc6i+eHpN77xX52kke3nq MIME-Version: 1.0 X-Received: by 10.60.60.131 with SMTP id h3mr2704714oer.17.1411030668018; Thu, 18 Sep 2014 01:57:48 -0700 (PDT) Received: by 10.202.13.21 with HTTP; Thu, 18 Sep 2014 01:57:47 -0700 (PDT) In-Reply-To: References: Date: Thu, 18 Sep 2014 10:57:47 +0200 Message-ID: From: David Marchand To: "Zhang, Helin" Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] i40e: Steps and required configurations of how to achieve the best performance! X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 18 Sep 2014 08:52:04 -0000 Hello Helin, On Thu, Sep 18, 2014 at 4:39 AM, Zhang, Helin wrote= : > Hi David > > > > *From:* David Marchand [mailto:david.marchand@6wind.com] > *Sent:* Wednesday, September 17, 2014 10:03 PM > *To:* Zhang, Helin > *Cc:* dev@dpdk.org > *Subject:* Re: [dpdk-dev] i40e: Steps and required configurations of how > to achieve the best performance! > > > > On Wed, Sep 17, 2014 at 10:50 AM, Zhang, Helin > wrote: > > For the =E2=80=98extended tag=E2=80=99, it was defined in PCIe spec, but= actually not > all BIOS implements it. Enabling it in BIOS or at runtime are two choices > of doing the same thing. I don=E2=80=99t think it can be configured per P= CI device > in BIOS, so we don=E2=80=99t need to do that per PCI device in DPDK. Righ= t? > Actually we don=E2=80=99t want to touch PCIe settings in DPDK code, that= =E2=80=99s why we > want to let BIOS config as it is by default. If no better choice, we can = do > it in DPDK by changing configurations. > > > > - Ok, then if we can make a runtime decision (at dpdk level), there is no > need for bios configuration and there is no need for a build option. > > Why don't we get rid of this option ? > > > > [Helin] Initially, we want to do that for BIOS, if specific BIOS does not > implement it. That way it needs to be initialized once during > initialization for each PCI device. Sure, that might not be the best > option, but it is the easiest way. For Linux end users, the best option > could be using =E2=80=98setpci=E2=80=99 command. It can enable =E2=80=98e= xtended_tag=E2=80=99 per PCI > device. > I am not sure I can see how easy it is since you are forcing this in a build option. Anyway, all this knowledge should be in the documentation and not in an obscure build option that looks to be useless in the end. The more I look at this, the more I think we did not have good enough argument for this change in eal / igb_uio yet. We have something that gives "better performance" on "some server" with "some bios". > > As far as the per-device runtime configuration is concerned, I want to > make sure this pci configuration will not break other "igb_uio" pci devic= es. > > If Intel can tell for sure this won't break other devices, then fine, we > can go and enable this for all "igb_uio" pci devices. > > > > [Helin] It is in PCIe specification, and enable it can provide better > performance generally. But I cannot confirm that it would not break any > other devices, as I don=E2=80=99t validate all devices. If you really con= cern it, > =E2=80=98setpci=E2=80=99 can be the best option for you. We can add a scr= ipt for that later. > Why not a script, but documentation is important too: I would say that we need an explicit list of platforms and nics which support this. > > - By the way, there is also the CONFIG_MAX_READ_REQUEST_SIZE option that > seems to be disabled (or at least its value 0 seems to tell so). > > What is its purpose ? > > > > [Helin] Yes, it was added for performance tuning long long ago. But now i= t > seems contribute nothing or too few for the performance number, so I just > skip it. The default value does nothing on PCIe registers, just keep it a= s > is. > Not so long ago to dpdk.org (somewhere around 1.7.0 ...). If this code had no use for "so long", why did it end up on dpdk.org ? Why should we keep it ? Thanks. --=20 David Marchand