From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ob0-f182.google.com (mail-ob0-f182.google.com [209.85.214.182]) by dpdk.org (Postfix) with ESMTP id E77732EDA for ; Fri, 6 Mar 2015 07:28:50 +0100 (CET) Received: by obbgq1 with SMTP id gq1so18940838obb.2 for ; Thu, 05 Mar 2015 22:28:50 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=J9fUOr4ga9yxXzFWuEEA8D2cDacWyEAK5phH/eIhn0E=; b=ALRYgHaPEfKg7Nf2hcmgflavw+/4ZnP6H7tR2n9HCgVnkwhPfC26tOb9V5UYTfz7hW /0GPuKz4JH3KOtGGtC4lSdWhXn5LTYvKOJmVYnFNxPydG0+xC+y3z7sXAc5KFQIM05Dt E/rE78T2E/BwQ9Gusqc6t/te5GB+Vwgt6qwMSG8uFf3inR4zH8tPtTnvH5nfEIMb6Kei K8UGYsBCMWZS9Uiz8+9Oh9xH2MpiQUXTqOg7lKwv1EWnrwlHFfO1YUk9pPnXLUu4VDjB JUujUifWeaW0ThIayJ9v5PWMDAESEs4IXNZ6Y/nBAOjYLvyjxGZ2AX5/pS64qL6tF/KC /5fg== X-Gm-Message-State: ALoCoQkqJySAVvYXf9ENyI5bT5dNQmdBgXwwQ7JziHdh+prOlXmKRD6a7Rc069elgZwMRFvZzk/C MIME-Version: 1.0 X-Received: by 10.60.155.135 with SMTP id vw7mr9957909oeb.62.1425623330197; Thu, 05 Mar 2015 22:28:50 -0800 (PST) Received: by 10.76.34.35 with HTTP; Thu, 5 Mar 2015 22:28:50 -0800 (PST) In-Reply-To: <1425563863-13712-1-git-send-email-michael.qiu@intel.com> References: <1425561339-13300-4-git-send-email-michael.qiu@intel.com> <1425563863-13712-1-git-send-email-michael.qiu@intel.com> Date: Fri, 6 Mar 2015 07:28:50 +0100 Message-ID: From: David Marchand To: Michael Qiu Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] =?utf-8?q?=5BPATCH_3/3_v3=5D_librte=5Feal/common=3A_Fi?= =?utf-8?q?x_redeclaration_of_enumerator_=E2=80=98REG=5FEAX=E2=80=99?= X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Mar 2015 06:28:51 -0000 On Thu, Mar 5, 2015 at 2:57 PM, Michael Qiu wrote: > include/rte_cpuflags.h:154:2: error: redeclaration of enumerator =E2=80= =98REG_EAX=E2=80=99 > In file included from /usr/include/signal.h:358:0, > from /usr/include/sys/wait.h:30, > from /root/dpdk/app/test/test_mp_secondary.c:50: > /usr/include/sys/ucontext.h:180:3: note: previous definition of =E2=80=98= REG_EAX=E2=80=99 > was here > > In i686, from REG_EAX to REG_EDX are all defined in > /usr/include/sys/ucontext.h > > Rename to CPU_REG_EAX to avoid this issue. > Thomas, - title must be fixed - commit log must be fixed :CPU_REG_EAX -> RTE_REG_EAX There is still some ambiguity in these macros names to me, but this is the quickest fix, so : Acked-by: David Marchand --=20 David Marchand > > Signed-off-by: Michael Qiu > --- > v3 --> v2: > Fix signed-off-by field > v2 --> v1: > rename CPU_REG_EAX to RTE_REG_EAX > > .../common/include/arch/x86/rte_cpuflags.h | 210 > ++++++++++----------- > 1 file changed, 105 insertions(+), 105 deletions(-) > > diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h > b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h > index a58dd7b..dd56553 100644 > --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h > +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h > @@ -151,104 +151,104 @@ enum rte_cpu_flag_t { > }; > > enum cpu_register_t { > - REG_EAX =3D 0, > - REG_EBX, > - REG_ECX, > - REG_EDX, > + RTE_REG_EAX =3D 0, > + RTE_REG_EBX, > + RTE_REG_ECX, > + RTE_REG_EDX, > }; > > static const struct feature_entry cpu_feature_table[] =3D { > - FEAT_DEF(SSE3, 0x00000001, 0, REG_ECX, 0) > - FEAT_DEF(PCLMULQDQ, 0x00000001, 0, REG_ECX, 1) > - FEAT_DEF(DTES64, 0x00000001, 0, REG_ECX, 2) > - FEAT_DEF(MONITOR, 0x00000001, 0, REG_ECX, 3) > - FEAT_DEF(DS_CPL, 0x00000001, 0, REG_ECX, 4) > - FEAT_DEF(VMX, 0x00000001, 0, REG_ECX, 5) > - FEAT_DEF(SMX, 0x00000001, 0, REG_ECX, 6) > - FEAT_DEF(EIST, 0x00000001, 0, REG_ECX, 7) > - FEAT_DEF(TM2, 0x00000001, 0, REG_ECX, 8) > - FEAT_DEF(SSSE3, 0x00000001, 0, REG_ECX, 9) > - FEAT_DEF(CNXT_ID, 0x00000001, 0, REG_ECX, 10) > - FEAT_DEF(FMA, 0x00000001, 0, REG_ECX, 12) > - FEAT_DEF(CMPXCHG16B, 0x00000001, 0, REG_ECX, 13) > - FEAT_DEF(XTPR, 0x00000001, 0, REG_ECX, 14) > - FEAT_DEF(PDCM, 0x00000001, 0, REG_ECX, 15) > - FEAT_DEF(PCID, 0x00000001, 0, REG_ECX, 17) > - FEAT_DEF(DCA, 0x00000001, 0, REG_ECX, 18) > - FEAT_DEF(SSE4_1, 0x00000001, 0, REG_ECX, 19) > - FEAT_DEF(SSE4_2, 0x00000001, 0, REG_ECX, 20) > - FEAT_DEF(X2APIC, 0x00000001, 0, REG_ECX, 21) > - FEAT_DEF(MOVBE, 0x00000001, 0, REG_ECX, 22) > - FEAT_DEF(POPCNT, 0x00000001, 0, REG_ECX, 23) > - FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, REG_ECX, 24) > - FEAT_DEF(AES, 0x00000001, 0, REG_ECX, 25) > - FEAT_DEF(XSAVE, 0x00000001, 0, REG_ECX, 26) > - FEAT_DEF(OSXSAVE, 0x00000001, 0, REG_ECX, 27) > - FEAT_DEF(AVX, 0x00000001, 0, REG_ECX, 28) > - FEAT_DEF(F16C, 0x00000001, 0, REG_ECX, 29) > - FEAT_DEF(RDRAND, 0x00000001, 0, REG_ECX, 30) > - > - FEAT_DEF(FPU, 0x00000001, 0, REG_EDX, 0) > - FEAT_DEF(VME, 0x00000001, 0, REG_EDX, 1) > - FEAT_DEF(DE, 0x00000001, 0, REG_EDX, 2) > - FEAT_DEF(PSE, 0x00000001, 0, REG_EDX, 3) > - FEAT_DEF(TSC, 0x00000001, 0, REG_EDX, 4) > - FEAT_DEF(MSR, 0x00000001, 0, REG_EDX, 5) > - FEAT_DEF(PAE, 0x00000001, 0, REG_EDX, 6) > - FEAT_DEF(MCE, 0x00000001, 0, REG_EDX, 7) > - FEAT_DEF(CX8, 0x00000001, 0, REG_EDX, 8) > - FEAT_DEF(APIC, 0x00000001, 0, REG_EDX, 9) > - FEAT_DEF(SEP, 0x00000001, 0, REG_EDX, 11) > - FEAT_DEF(MTRR, 0x00000001, 0, REG_EDX, 12) > - FEAT_DEF(PGE, 0x00000001, 0, REG_EDX, 13) > - FEAT_DEF(MCA, 0x00000001, 0, REG_EDX, 14) > - FEAT_DEF(CMOV, 0x00000001, 0, REG_EDX, 15) > - FEAT_DEF(PAT, 0x00000001, 0, REG_EDX, 16) > - FEAT_DEF(PSE36, 0x00000001, 0, REG_EDX, 17) > - FEAT_DEF(PSN, 0x00000001, 0, REG_EDX, 18) > - FEAT_DEF(CLFSH, 0x00000001, 0, REG_EDX, 19) > - FEAT_DEF(DS, 0x00000001, 0, REG_EDX, 21) > - FEAT_DEF(ACPI, 0x00000001, 0, REG_EDX, 22) > - FEAT_DEF(MMX, 0x00000001, 0, REG_EDX, 23) > - FEAT_DEF(FXSR, 0x00000001, 0, REG_EDX, 24) > - FEAT_DEF(SSE, 0x00000001, 0, REG_EDX, 25) > - FEAT_DEF(SSE2, 0x00000001, 0, REG_EDX, 26) > - FEAT_DEF(SS, 0x00000001, 0, REG_EDX, 27) > - FEAT_DEF(HTT, 0x00000001, 0, REG_EDX, 28) > - FEAT_DEF(TM, 0x00000001, 0, REG_EDX, 29) > - FEAT_DEF(PBE, 0x00000001, 0, REG_EDX, 31) > - > - FEAT_DEF(DIGTEMP, 0x00000006, 0, REG_EAX, 0) > - FEAT_DEF(TRBOBST, 0x00000006, 0, REG_EAX, 1) > - FEAT_DEF(ARAT, 0x00000006, 0, REG_EAX, 2) > - FEAT_DEF(PLN, 0x00000006, 0, REG_EAX, 4) > - FEAT_DEF(ECMD, 0x00000006, 0, REG_EAX, 5) > - FEAT_DEF(PTM, 0x00000006, 0, REG_EAX, 6) > - > - FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, REG_ECX, 0) > - FEAT_DEF(ACNT2, 0x00000006, 0, REG_ECX, 1) > - FEAT_DEF(ENERGY_EFF, 0x00000006, 0, REG_ECX, 3) > - > - FEAT_DEF(FSGSBASE, 0x00000007, 0, REG_EBX, 0) > - FEAT_DEF(BMI1, 0x00000007, 0, REG_EBX, 2) > - FEAT_DEF(HLE, 0x00000007, 0, REG_EBX, 4) > - FEAT_DEF(AVX2, 0x00000007, 0, REG_EBX, 5) > - FEAT_DEF(SMEP, 0x00000007, 0, REG_EBX, 6) > - FEAT_DEF(BMI2, 0x00000007, 0, REG_EBX, 7) > - FEAT_DEF(ERMS, 0x00000007, 0, REG_EBX, 8) > - FEAT_DEF(INVPCID, 0x00000007, 0, REG_EBX, 10) > - FEAT_DEF(RTM, 0x00000007, 0, REG_EBX, 11) > - > - FEAT_DEF(LAHF_SAHF, 0x80000001, 0, REG_ECX, 0) > - FEAT_DEF(LZCNT, 0x80000001, 0, REG_ECX, 4) > - > - FEAT_DEF(SYSCALL, 0x80000001, 0, REG_EDX, 11) > - FEAT_DEF(XD, 0x80000001, 0, REG_EDX, 20) > - FEAT_DEF(1GB_PG, 0x80000001, 0, REG_EDX, 26) > - FEAT_DEF(RDTSCP, 0x80000001, 0, REG_EDX, 27) > - FEAT_DEF(EM64T, 0x80000001, 0, REG_EDX, 29) > - > - FEAT_DEF(INVTSC, 0x80000007, 0, REG_EDX, 8) > + FEAT_DEF(SSE3, 0x00000001, 0, RTE_REG_ECX, 0) > + FEAT_DEF(PCLMULQDQ, 0x00000001, 0, RTE_REG_ECX, 1) > + FEAT_DEF(DTES64, 0x00000001, 0, RTE_REG_ECX, 2) > + FEAT_DEF(MONITOR, 0x00000001, 0, RTE_REG_ECX, 3) > + FEAT_DEF(DS_CPL, 0x00000001, 0, RTE_REG_ECX, 4) > + FEAT_DEF(VMX, 0x00000001, 0, RTE_REG_ECX, 5) > + FEAT_DEF(SMX, 0x00000001, 0, RTE_REG_ECX, 6) > + FEAT_DEF(EIST, 0x00000001, 0, RTE_REG_ECX, 7) > + FEAT_DEF(TM2, 0x00000001, 0, RTE_REG_ECX, 8) > + FEAT_DEF(SSSE3, 0x00000001, 0, RTE_REG_ECX, 9) > + FEAT_DEF(CNXT_ID, 0x00000001, 0, RTE_REG_ECX, 10) > + FEAT_DEF(FMA, 0x00000001, 0, RTE_REG_ECX, 12) > + FEAT_DEF(CMPXCHG16B, 0x00000001, 0, RTE_REG_ECX, 13) > + FEAT_DEF(XTPR, 0x00000001, 0, RTE_REG_ECX, 14) > + FEAT_DEF(PDCM, 0x00000001, 0, RTE_REG_ECX, 15) > + FEAT_DEF(PCID, 0x00000001, 0, RTE_REG_ECX, 17) > + FEAT_DEF(DCA, 0x00000001, 0, RTE_REG_ECX, 18) > + FEAT_DEF(SSE4_1, 0x00000001, 0, RTE_REG_ECX, 19) > + FEAT_DEF(SSE4_2, 0x00000001, 0, RTE_REG_ECX, 20) > + FEAT_DEF(X2APIC, 0x00000001, 0, RTE_REG_ECX, 21) > + FEAT_DEF(MOVBE, 0x00000001, 0, RTE_REG_ECX, 22) > + FEAT_DEF(POPCNT, 0x00000001, 0, RTE_REG_ECX, 23) > + FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, RTE_REG_ECX, 24) > + FEAT_DEF(AES, 0x00000001, 0, RTE_REG_ECX, 25) > + FEAT_DEF(XSAVE, 0x00000001, 0, RTE_REG_ECX, 26) > + FEAT_DEF(OSXSAVE, 0x00000001, 0, RTE_REG_ECX, 27) > + FEAT_DEF(AVX, 0x00000001, 0, RTE_REG_ECX, 28) > + FEAT_DEF(F16C, 0x00000001, 0, RTE_REG_ECX, 29) > + FEAT_DEF(RDRAND, 0x00000001, 0, RTE_REG_ECX, 30) > + > + FEAT_DEF(FPU, 0x00000001, 0, RTE_REG_EDX, 0) > + FEAT_DEF(VME, 0x00000001, 0, RTE_REG_EDX, 1) > + FEAT_DEF(DE, 0x00000001, 0, RTE_REG_EDX, 2) > + FEAT_DEF(PSE, 0x00000001, 0, RTE_REG_EDX, 3) > + FEAT_DEF(TSC, 0x00000001, 0, RTE_REG_EDX, 4) > + FEAT_DEF(MSR, 0x00000001, 0, RTE_REG_EDX, 5) > + FEAT_DEF(PAE, 0x00000001, 0, RTE_REG_EDX, 6) > + FEAT_DEF(MCE, 0x00000001, 0, RTE_REG_EDX, 7) > + FEAT_DEF(CX8, 0x00000001, 0, RTE_REG_EDX, 8) > + FEAT_DEF(APIC, 0x00000001, 0, RTE_REG_EDX, 9) > + FEAT_DEF(SEP, 0x00000001, 0, RTE_REG_EDX, 11) > + FEAT_DEF(MTRR, 0x00000001, 0, RTE_REG_EDX, 12) > + FEAT_DEF(PGE, 0x00000001, 0, RTE_REG_EDX, 13) > + FEAT_DEF(MCA, 0x00000001, 0, RTE_REG_EDX, 14) > + FEAT_DEF(CMOV, 0x00000001, 0, RTE_REG_EDX, 15) > + FEAT_DEF(PAT, 0x00000001, 0, RTE_REG_EDX, 16) > + FEAT_DEF(PSE36, 0x00000001, 0, RTE_REG_EDX, 17) > + FEAT_DEF(PSN, 0x00000001, 0, RTE_REG_EDX, 18) > + FEAT_DEF(CLFSH, 0x00000001, 0, RTE_REG_EDX, 19) > + FEAT_DEF(DS, 0x00000001, 0, RTE_REG_EDX, 21) > + FEAT_DEF(ACPI, 0x00000001, 0, RTE_REG_EDX, 22) > + FEAT_DEF(MMX, 0x00000001, 0, RTE_REG_EDX, 23) > + FEAT_DEF(FXSR, 0x00000001, 0, RTE_REG_EDX, 24) > + FEAT_DEF(SSE, 0x00000001, 0, RTE_REG_EDX, 25) > + FEAT_DEF(SSE2, 0x00000001, 0, RTE_REG_EDX, 26) > + FEAT_DEF(SS, 0x00000001, 0, RTE_REG_EDX, 27) > + FEAT_DEF(HTT, 0x00000001, 0, RTE_REG_EDX, 28) > + FEAT_DEF(TM, 0x00000001, 0, RTE_REG_EDX, 29) > + FEAT_DEF(PBE, 0x00000001, 0, RTE_REG_EDX, 31) > + > + FEAT_DEF(DIGTEMP, 0x00000006, 0, RTE_REG_EAX, 0) > + FEAT_DEF(TRBOBST, 0x00000006, 0, RTE_REG_EAX, 1) > + FEAT_DEF(ARAT, 0x00000006, 0, RTE_REG_EAX, 2) > + FEAT_DEF(PLN, 0x00000006, 0, RTE_REG_EAX, 4) > + FEAT_DEF(ECMD, 0x00000006, 0, RTE_REG_EAX, 5) > + FEAT_DEF(PTM, 0x00000006, 0, RTE_REG_EAX, 6) > + > + FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, RTE_REG_ECX, 0) > + FEAT_DEF(ACNT2, 0x00000006, 0, RTE_REG_ECX, 1) > + FEAT_DEF(ENERGY_EFF, 0x00000006, 0, RTE_REG_ECX, 3) > + > + FEAT_DEF(FSGSBASE, 0x00000007, 0, RTE_REG_EBX, 0) > + FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX, 2) > + FEAT_DEF(HLE, 0x00000007, 0, RTE_REG_EBX, 4) > + FEAT_DEF(AVX2, 0x00000007, 0, RTE_REG_EBX, 5) > + FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX, 6) > + FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX, 7) > + FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX, 8) > + FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10) > + FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11) > + > + FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0) > + FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4) > + > + FEAT_DEF(SYSCALL, 0x80000001, 0, RTE_REG_EDX, 11) > + FEAT_DEF(XD, 0x80000001, 0, RTE_REG_EDX, 20) > + FEAT_DEF(1GB_PG, 0x80000001, 0, RTE_REG_EDX, 26) > + FEAT_DEF(RDTSCP, 0x80000001, 0, RTE_REG_EDX, 27) > + FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29) > + > + FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX, 8) > }; > > static inline void > @@ -257,18 +257,18 @@ rte_cpu_get_features(uint32_t leaf, uint32_t > subleaf, cpuid_registers_t out) > #if defined(__i386__) && defined(__PIC__) > /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */ > asm volatile("movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0" > - : "=3Dr" (out[REG_EBX]), > - "=3Da" (out[REG_EAX]), > - "=3Dc" (out[REG_ECX]), > - "=3Dd" (out[REG_EDX]) > + : "=3Dr" (out[RTE_REG_EBX]), > + "=3Da" (out[RTE_REG_EAX]), > + "=3Dc" (out[RTE_REG_ECX]), > + "=3Dd" (out[RTE_REG_EDX]) > : "a" (leaf), "c" (subleaf)); > #else > > asm volatile("cpuid" > - : "=3Da" (out[REG_EAX]), > - "=3Db" (out[REG_EBX]), > - "=3Dc" (out[REG_ECX]), > - "=3Dd" (out[REG_EDX]) > + : "=3Da" (out[RTE_REG_EAX]), > + "=3Db" (out[RTE_REG_EBX]), > + "=3Dc" (out[RTE_REG_ECX]), > + "=3Dd" (out[RTE_REG_EDX]) > : "a" (leaf), "c" (subleaf)); > > #endif > @@ -292,8 +292,8 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) > return -EFAULT; > > rte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs); > - if (((regs[REG_EAX] ^ feat->leaf) & 0xffff0000) || > - regs[REG_EAX] < feat->leaf) > + if (((regs[RTE_REG_EAX] ^ feat->leaf) & 0xffff0000) || > + regs[RTE_REG_EAX] < feat->leaf) > return 0; > > /* get the cpuid leaf containing the desired feature */ > -- > 1.9.3 > >