From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8AD8241C62; Sat, 11 Feb 2023 00:47:44 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1BB2F40E50; Sat, 11 Feb 2023 00:47:44 +0100 (CET) Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) by mails.dpdk.org (Postfix) with ESMTP id 772EF40E0F for ; Sat, 11 Feb 2023 00:47:42 +0100 (CET) Received: by mail-ed1-f41.google.com with SMTP id d40so5023742eda.8 for ; Fri, 10 Feb 2023 15:47:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=atomicrules-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=VQU1QDA/BahtCYtfQwd4ligwsIpHAu/y8xxztPYyALo=; b=UesDttQzekpQZs9myokKU5kfoGEZZqMw71JbjxefkxMWb6TNTy1qwXJpUHEPgY0SO7 UL13e3XCy1HG24a3RW52iCgF6PL3W01yNRIaOwtPHmVe4303C5uEtVKG4kbBcpl8FLpH cBrUEi6B+KTe3qS20GytOJSVKgzOGwueVyhzIHk4RUbGA9miPDNr9RQyNKTS61FYFiF1 GxvNqP/CStz5t5FNHsr7nauFRl0EaBjX0M414LNGzK/C15BzCgT8kI0rx58i9tr60Hoc DyazcgfxHakjK7UThOgOnZcLNnmzWrQpPQ2KwqfYCuxB9pWMdBrZ/kAl9kF92RRU32ba LIZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=VQU1QDA/BahtCYtfQwd4ligwsIpHAu/y8xxztPYyALo=; b=pbYRbYaoqdcUYga1E9oOFAf/1Bb0aHRopPUiZzukL/PYEL5Lb2LEJPUAIgJCl6WfM1 iBbUX64DoWC1c6Bg33fbI87RZ+92dcNpByftxuM3OvGMMjpwqttaPE6Me9rzwR3zWnaK Z+V0J4vtJhVnIf/V67gSUBQq4dBjaF/MngNU6xbbAdfucWRTcxs5w41a79lTc38FZ15v fcrLstZz1p3+PQbAEtoUNCLs3FVsC+imV6qUPpV1SU7f3HBIfqz8gPUqmquXR/54buJq lJEBdl9A4MkNggwsaWCNMjxAjZrlIei0QCQXsUAQmuSU0fbalfxncN9vQ6yusIIVZfZQ 8FKQ== X-Gm-Message-State: AO0yUKUp+0rXDc0XbMfPcp+nUdrnQo+6iyK+A36FZvHkg0kCmapDJ5nV 9LxJpj9cZ9YfArgg1Qc4JNq+tQ37X07rLyAzxE8FgxuvrN+VcA== X-Google-Smtp-Source: AK7set8ludZxoC8Hm9lAfj8EstkuNE5aT83Avg+ErEekCGx2lhL3Lkp8bO9rXlXEkiafb9WH/SQ0GPLcAFxFH1WnI+o= X-Received: by 2002:a50:99cd:0:b0:4ab:eac:30fa with SMTP id n13-20020a5099cd000000b004ab0eac30famr2623233edb.3.1676072862058; Fri, 10 Feb 2023 15:47:42 -0800 (PST) MIME-Version: 1.0 References: <20230210193837.2604100-1-shepard.siegel@atomicrules.com> <20230210223517.2606357-1-shepard.siegel@atomicrules.com> In-Reply-To: From: Shepard Siegel Date: Fri, 10 Feb 2023 18:47:31 -0500 Message-ID: Subject: Re: [PATCH v2] doc: update ark guide To: Ferruh Yigit Cc: ed.czeck@atomicrules.com, dev@dpdk.org Content-Type: multipart/alternative; boundary="0000000000008fa39e05f4611f01" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org --0000000000008fa39e05f4611f01 Content-Type: text/plain; charset="UTF-8" Thank you Ferruh, I understand now. We will abandon this patch and do exactly as you suggest with two separate patches. Thanks for your guidance. Look for the two patches ETA tomorrow. -Shep On Fri, Feb 10, 2023 at 5:56 PM Ferruh Yigit wrote: > On 2/10/2023 10:35 PM, Shepard Siegel wrote: > > Add ark PCIe device 1d6c:1022 FX2 to pci_id_ark_map. > > Include introduced FX2 PCIe ID and description. > > > > Thanks for v2, but this is no more just a documentation patch, > can you please split the patch into two, > first one adds new device support and update documentation related to > new device, with a 'net/ark:' title, > second one updates the document for extended information which is most > of this patch > > > > Signed-off-by: Shepard Siegel > > --- > > doc/guides/nics/ark.rst | 20 ++++++++++++++++++++ > > drivers/net/ark/ark_ethdev.c | 1 + > > 2 files changed, 21 insertions(+) > > > > diff --git a/doc/guides/nics/ark.rst b/doc/guides/nics/ark.rst > > index ba00f14e80..39cd75064d 100644 > > --- a/doc/guides/nics/ark.rst > > +++ b/doc/guides/nics/ark.rst > > @@ -52,6 +52,10 @@ board. While specific capabilities such as number of > physical > > hardware queue-pairs are negotiated; the driver is designed to > > remain constant over a broad and extendable feature set. > > > > +* FPGA Vendors Supported: AMD/Xilinx and Intel > > +* Number of RX/TX Queue-Pairs: up to 128 > > +* PCIe Endpoint Technology: Gen3, Gen4, Gen5 > > + > > Intentionally, Arkville by itself DOES NOT provide common NIC > > capabilities such as offload or receive-side scaling (RSS). > > These capabilities would be viewed as a gate-level "tax" on > > @@ -302,6 +306,20 @@ ARK PMD supports the following Arkville RTL PCIe > instances including: > > * ``1d6c:101c`` - AR-ARK-SRIOV-VF [Arkville Virtual Function] > > * ``1d6c:101e`` - AR-ARKA-FX1 [Arkville 64B DPDK Data Mover for Agilex > R-Tile] > > * ``1d6c:101f`` - AR-TK242 [2x100GbE Packet Capture Device] > > +* ``1d6c:1022`` - AR-ARKA-FX2 [Arkville 128B DPDK Data Mover for Agilex] > > + > > +Arkville RTL Core Configurations > > +------------------------------------- > > + > > +Arkville's RTL core may be configured by the user for three different > > +datapath widths to balance throughput against FPGA logic area. The ARK > PMD > > +has introspection on the RTL core configuration and acts accordingly. > > +All three configurations present identical RTL user-facing AXI stream > > +interfaces for both AMD/Xilinx and Intel FPGAs. > > + > > +* ARK-FX0 - 256-bit 32B datapath (PCIe Gen3, Gen4) > > +* ARK-FX1 - 512-bit 64B datapath (PCIe Gen3, Gen4, Gen5) > > +* ARK-FX2 - 1024-bit 128B datapath (PCIe Gen5x16 Only) > > > > DPDK and Arkville Firmware Versioning > > ------------------------------------- > > @@ -334,6 +352,8 @@ Supported Features > > ------------------ > > > > * Dynamic ARK PMD extensions > > +* Dynamic per-queue MBUF (re)sizing up to 32KB > > +* SR-IOV, VF-based queue-segregation > > * Multiple receive and transmit queues > > * Jumbo frames up to 9K > > * Hardware Statistics > > diff --git a/drivers/net/ark/ark_ethdev.c b/drivers/net/ark/ark_ethdev.c > > index c654a229f7..b2995427c8 100644 > > --- a/drivers/net/ark/ark_ethdev.c > > +++ b/drivers/net/ark/ark_ethdev.c > > @@ -99,6 +99,7 @@ static const struct rte_pci_id pci_id_ark_map[] = { > > {RTE_PCI_DEVICE(AR_VENDOR_ID, 0x101c)}, > > {RTE_PCI_DEVICE(AR_VENDOR_ID, 0x101e)}, > > {RTE_PCI_DEVICE(AR_VENDOR_ID, 0x101f)}, > > + {RTE_PCI_DEVICE(AR_VENDOR_ID, 0x1022)}, > > {.vendor_id = 0, /* sentinel */ }, > > }; > > > > --0000000000008fa39e05f4611f01 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Thank you Ferruh,
I understand now.
We will = abandon this patch and do exactly=C2=A0as you suggest with two separate=C2= =A0patches.
Thanks for your guidance. Look for the two patches ET= A tomorrow.
-Shep

On Fri, Feb 10, 2023 at 5:56 PM Ferruh Yig= it <ferruh.yigit@amd.com>= wrote:
On 2/10/= 2023 10:35 PM, Shepard Siegel wrote:
> Add ark PCIe device 1d6c:1022 FX2 to pci_id_ark_map.
> Include introduced FX2 PCIe ID and description.
>

Thanks for v2, but this is no more just a documentation patch,
can you please split the patch into two,
first one adds new device support and update documentation related to
new device, with a 'net/ark:' title,
second one updates the document for extended information which is most
of this patch


> Signed-off-by: Shepard Siegel <shepard.siegel@atomicrules.com>
> ---
>=C2=A0 doc/guides/nics/ark.rst=C2=A0 =C2=A0 =C2=A0 | 20 +++++++++++++++= +++++
>=C2=A0 drivers/net/ark/ark_ethdev.c |=C2=A0 1 +
>=C2=A0 2 files changed, 21 insertions(+)
>
> diff --git a/doc/guides/nics/ark.rst b/doc/guides/nics/ark.rst
> index ba00f14e80..39cd75064d 100644
> --- a/doc/guides/nics/ark.rst
> +++ b/doc/guides/nics/ark.rst
> @@ -52,6 +52,10 @@ board. While specific capabilities such as number o= f physical
>=C2=A0 hardware queue-pairs are negotiated; the driver is designed to >=C2=A0 remain constant over a broad and extendable feature set.
>=C2=A0
> +* FPGA Vendors Supported: AMD/Xilinx and Intel
> +* Number of RX/TX Queue-Pairs: up to 128
> +* PCIe Endpoint Technology: Gen3, Gen4, Gen5
> +
>=C2=A0 Intentionally, Arkville by itself DOES NOT provide common NIC >=C2=A0 capabilities such as offload or receive-side scaling (RSS).
>=C2=A0 These capabilities would be viewed as a gate-level "tax&quo= t; on
> @@ -302,6 +306,20 @@ ARK PMD supports the following Arkville RTL PCIe = instances including:
>=C2=A0 * ``1d6c:101c`` - AR-ARK-SRIOV-VF [Arkville Virtual Function] >=C2=A0 * ``1d6c:101e`` - AR-ARKA-FX1 [Arkville 64B DPDK Data Mover for = Agilex R-Tile]
>=C2=A0 * ``1d6c:101f`` - AR-TK242 [2x100GbE Packet Capture Device]
> +* ``1d6c:1022`` - AR-ARKA-FX2 [Arkville 128B DPDK Data Mover for Agil= ex]
> +
> +Arkville RTL Core Configurations
> +-------------------------------------
> +
> +Arkville's RTL core may be configured by the user for three diffe= rent
> +datapath widths to balance throughput against FPGA logic area. The AR= K PMD
> +has introspection on the RTL core configuration and acts accordingly.=
> +All three configurations present identical RTL user-facing AXI stream=
> +interfaces for both AMD/Xilinx and Intel FPGAs.
> +
> +* ARK-FX0 - 256-bit 32B datapath (PCIe Gen3, Gen4)
> +* ARK-FX1 - 512-bit 64B datapath (PCIe Gen3, Gen4, Gen5)
> +* ARK-FX2 - 1024-bit 128B datapath (PCIe Gen5x16 Only)
>=C2=A0
>=C2=A0 DPDK and Arkville Firmware Versioning
>=C2=A0 -------------------------------------
> @@ -334,6 +352,8 @@ Supported Features
>=C2=A0 ------------------
>=C2=A0
>=C2=A0 * Dynamic ARK PMD extensions
> +* Dynamic per-queue MBUF (re)sizing up to 32KB
> +* SR-IOV, VF-based queue-segregation
>=C2=A0 * Multiple receive and transmit queues
>=C2=A0 * Jumbo frames up to 9K
>=C2=A0 * Hardware Statistics
> diff --git a/drivers/net/ark/ark_ethdev.c b/drivers/net/ark/ark_ethdev= .c
> index c654a229f7..b2995427c8 100644
> --- a/drivers/net/ark/ark_ethdev.c
> +++ b/drivers/net/ark/ark_ethdev.c
> @@ -99,6 +99,7 @@ static const struct rte_pci_id pci_id_ark_map[] =3D = {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0{RTE_PCI_DEVICE(AR_VENDOR_ID, 0x101c)},
>=C2=A0 =C2=A0 =C2=A0 =C2=A0{RTE_PCI_DEVICE(AR_VENDOR_ID, 0x101e)},
>=C2=A0 =C2=A0 =C2=A0 =C2=A0{RTE_PCI_DEVICE(AR_VENDOR_ID, 0x101f)},
> +=C2=A0 =C2=A0 =C2=A0{RTE_PCI_DEVICE(AR_VENDOR_ID, 0x1022)},
>=C2=A0 =C2=A0 =C2=A0 =C2=A0{.vendor_id =3D 0, /* sentinel */ },
>=C2=A0 };
>=C2=A0

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