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References: <20230509030729.2680451-1-junfeng.guo@intel.com>
In-Reply-To: <20230509030729.2680451-1-junfeng.guo@intel.com>
From: Rushil Gupta <rushilg@google.com>
Date: Mon, 15 May 2023 13:28:35 -0700
Message-ID: <CANzqiF4DhEhz+ugdLL6PU_6TxnDh81z-s=szb_DiOSij4TsEXg@mail.gmail.com>
Subject: Re: [PATCH] net/gve: support queue start and stop operations
To: Junfeng Guo <junfeng.guo@intel.com>
Cc: qi.z.zhang@intel.com, ferruh.yigit@amd.com, dev@dpdk.org, 
 joshwash@google.com, jeroendb@google.com
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tested-by: Rushil Gupta <rushilg@google.com>

On Mon, May 8, 2023 at 8:07=E2=80=AFPM Junfeng Guo <junfeng.guo@intel.com> =
wrote:

> Add support for queue operations for GQI:
>  - gve_rx_queue_start
>  - gve_tx_queue_start
>  - gve_rx_queue_stop
>  - gve_tx_queue_stop
>
> Add support for queue operations for DQO:
>  - gve_rx_queue_start_dqo
>  - gve_tx_queue_start_dqo
>  - gve_rx_queue_stop_dqo
>  - gve_tx_queue_stop_dqo
>
> Also move the funcs of rxq_mbufs_alloc into the corresponding files.
>
> Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
> ---
>  drivers/net/gve/gve_ethdev.c | 166 +++++++++++------------------------
>  drivers/net/gve/gve_ethdev.h |  36 ++++++++
>  drivers/net/gve/gve_rx.c     |  96 ++++++++++++++++++--
>  drivers/net/gve/gve_rx_dqo.c |  97 ++++++++++++++++++--
>  drivers/net/gve/gve_tx.c     |  54 ++++++++++--
>  drivers/net/gve/gve_tx_dqo.c |  54 ++++++++++--
>  6 files changed, 364 insertions(+), 139 deletions(-)
>
> diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c
> index 8b6861a24f..1dcb3b3a01 100644
> --- a/drivers/net/gve/gve_ethdev.c
> +++ b/drivers/net/gve/gve_ethdev.c
> @@ -104,81 +104,6 @@ gve_dev_configure(struct rte_eth_dev *dev)
>         return 0;
>  }
>
> -static int
> -gve_refill_pages(struct gve_rx_queue *rxq)
> -{
> -       struct rte_mbuf *nmb;
> -       uint16_t i;
> -       int diag;
> -
> -       diag =3D rte_pktmbuf_alloc_bulk(rxq->mpool, &rxq->sw_ring[0],
> rxq->nb_rx_desc);
> -       if (diag < 0) {
> -               for (i =3D 0; i < rxq->nb_rx_desc - 1; i++) {
> -                       nmb =3D rte_pktmbuf_alloc(rxq->mpool);
> -                       if (!nmb)
> -                               break;
> -                       rxq->sw_ring[i] =3D nmb;
> -               }
> -               if (i < rxq->nb_rx_desc - 1)
> -                       return -ENOMEM;
> -       }
> -       rxq->nb_avail =3D 0;
> -       rxq->next_avail =3D rxq->nb_rx_desc - 1;
> -
> -       for (i =3D 0; i < rxq->nb_rx_desc; i++) {
> -               if (rxq->is_gqi_qpl) {
> -                       rxq->rx_data_ring[i].addr =3D rte_cpu_to_be_64(i =
*
> PAGE_SIZE);
> -               } else {
> -                       if (i =3D=3D rxq->nb_rx_desc - 1)
> -                               break;
> -                       nmb =3D rxq->sw_ring[i];
> -                       rxq->rx_data_ring[i].addr =3D
> rte_cpu_to_be_64(rte_mbuf_data_iova(nmb));
> -               }
> -       }
> -
> -       rte_write32(rte_cpu_to_be_32(rxq->next_avail), rxq->qrx_tail);
> -
> -       return 0;
> -}
> -
> -static int
> -gve_refill_dqo(struct gve_rx_queue *rxq)
> -{
> -       struct rte_mbuf *nmb;
> -       uint16_t i;
> -       int diag;
> -
> -       diag =3D rte_pktmbuf_alloc_bulk(rxq->mpool, &rxq->sw_ring[0],
> rxq->nb_rx_desc);
> -       if (diag < 0) {
> -               rxq->stats.no_mbufs_bulk++;
> -               for (i =3D 0; i < rxq->nb_rx_desc - 1; i++) {
> -                       nmb =3D rte_pktmbuf_alloc(rxq->mpool);
> -                       if (!nmb)
> -                               break;
> -                       rxq->sw_ring[i] =3D nmb;
> -               }
> -               if (i < rxq->nb_rx_desc - 1) {
> -                       rxq->stats.no_mbufs +=3D rxq->nb_rx_desc - 1 - i;
> -                       return -ENOMEM;
> -               }
> -       }
> -
> -       for (i =3D 0; i < rxq->nb_rx_desc; i++) {
> -               if (i =3D=3D rxq->nb_rx_desc - 1)
> -                       break;
> -               nmb =3D rxq->sw_ring[i];
> -               rxq->rx_ring[i].buf_addr =3D
> rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
> -               rxq->rx_ring[i].buf_id =3D rte_cpu_to_le_16(i);
> -       }
> -
> -       rxq->nb_rx_hold =3D 0;
> -       rxq->bufq_tail =3D rxq->nb_rx_desc - 1;
> -
> -       rte_write32(rxq->bufq_tail, rxq->qrx_tail);
> -
> -       return 0;
> -}
> -
>  static int
>  gve_link_update(struct rte_eth_dev *dev, __rte_unused int
> wait_to_complete)
>  {
> @@ -208,65 +133,68 @@ gve_link_update(struct rte_eth_dev *dev,
> __rte_unused int wait_to_complete)
>  }
>
>  static int
> -gve_dev_start(struct rte_eth_dev *dev)
> +gve_start_queues(struct rte_eth_dev *dev)
>  {
> -       uint16_t num_queues =3D dev->data->nb_tx_queues;
>         struct gve_priv *priv =3D dev->data->dev_private;
> -       struct gve_tx_queue *txq;
> -       struct gve_rx_queue *rxq;
> +       uint16_t num_queues;
>         uint16_t i;
> -       int err;
> +       int ret;
>
> +       num_queues =3D dev->data->nb_tx_queues;
>         priv->txqs =3D (struct gve_tx_queue **)dev->data->tx_queues;
> -       err =3D gve_adminq_create_tx_queues(priv, num_queues);
> -       if (err) {
> -               PMD_DRV_LOG(ERR, "failed to create %u tx queues.",
> num_queues);
> -               return err;
> -       }
> -       for (i =3D 0; i < num_queues; i++) {
> -               txq =3D priv->txqs[i];
> -               txq->qtx_tail =3D
> -               &priv->db_bar2[rte_be_to_cpu_32(txq->qres->db_index)];
> -               txq->qtx_head =3D
> -
>  &priv->cnt_array[rte_be_to_cpu_32(txq->qres->counter_index)];
> -
> -               rte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK),
> txq->ntfy_addr);
> -       }
> +       ret =3D gve_adminq_create_tx_queues(priv, num_queues);
> +       if (ret !=3D 0) {
> +               PMD_DRV_LOG(ERR, "Failed to create %u tx queues.",
> num_queues);
> +               return ret;
> +       }
> +       for (i =3D 0; i < num_queues; i++)
> +               if (gve_tx_queue_start(dev, i) !=3D 0) {
> +                       PMD_DRV_LOG(ERR, "Fail to start Tx queue %d", i);
> +                       goto err_tx;
> +               }
>
>         num_queues =3D dev->data->nb_rx_queues;
>         priv->rxqs =3D (struct gve_rx_queue **)dev->data->rx_queues;
> -       err =3D gve_adminq_create_rx_queues(priv, num_queues);
> -       if (err) {
> -               PMD_DRV_LOG(ERR, "failed to create %u rx queues.",
> num_queues);
> +       ret =3D gve_adminq_create_rx_queues(priv, num_queues);
> +       if (ret !=3D 0) {
> +               PMD_DRV_LOG(ERR, "Failed to create %u rx queues.",
> num_queues);
>                 goto err_tx;
>         }
>         for (i =3D 0; i < num_queues; i++) {
> -               rxq =3D priv->rxqs[i];
> -               rxq->qrx_tail =3D
> -               &priv->db_bar2[rte_be_to_cpu_32(rxq->qres->db_index)];
> -
> -               rte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK),
> rxq->ntfy_addr);
> -
>                 if (gve_is_gqi(priv))
> -                       err =3D gve_refill_pages(rxq);
> +                       ret =3D gve_rx_queue_start(dev, i);
>                 else
> -                       err =3D gve_refill_dqo(rxq);
> -               if (err) {
> -                       PMD_DRV_LOG(ERR, "Failed to refill for RX");
> +                       ret =3D gve_rx_queue_start_dqo(dev, i);
> +               if (ret !=3D 0) {
> +                       PMD_DRV_LOG(ERR, "Fail to start Rx queue %d", i);
>                         goto err_rx;
>                 }
>         }
>
> -       dev->data->dev_started =3D 1;
> -       gve_link_update(dev, 0);
> -
>         return 0;
>
>  err_rx:
>         gve_stop_rx_queues(dev);
>  err_tx:
>         gve_stop_tx_queues(dev);
> -       return err;
> +       return ret;
> +}
> +
> +static int
> +gve_dev_start(struct rte_eth_dev *dev)
> +{
> +       int ret;
> +
> +       ret =3D gve_start_queues(dev);
> +       if (ret !=3D 0) {
> +               PMD_DRV_LOG(ERR, "Failed to start queues");
> +               return ret;
> +       }
> +
> +       dev->data->dev_started =3D 1;
> +       gve_link_update(dev, 0);
> +
> +       return 0;
>  }
>
>  static int
> @@ -573,6 +501,10 @@ static const struct eth_dev_ops gve_eth_dev_ops =3D =
{
>         .tx_queue_setup       =3D gve_tx_queue_setup,
>         .rx_queue_release     =3D gve_rx_queue_release,
>         .tx_queue_release     =3D gve_tx_queue_release,
> +       .rx_queue_start       =3D gve_rx_queue_start,
> +       .tx_queue_start       =3D gve_tx_queue_start,
> +       .rx_queue_stop        =3D gve_rx_queue_stop,
> +       .tx_queue_stop        =3D gve_tx_queue_stop,
>         .link_update          =3D gve_link_update,
>         .stats_get            =3D gve_dev_stats_get,
>         .stats_reset          =3D gve_dev_stats_reset,
> @@ -591,6 +523,10 @@ static const struct eth_dev_ops gve_eth_dev_ops_dqo =
=3D
> {
>         .tx_queue_setup       =3D gve_tx_queue_setup_dqo,
>         .rx_queue_release     =3D gve_rx_queue_release_dqo,
>         .tx_queue_release     =3D gve_tx_queue_release_dqo,
> +       .rx_queue_start       =3D gve_rx_queue_start_dqo,
> +       .tx_queue_start       =3D gve_tx_queue_start_dqo,
> +       .rx_queue_stop        =3D gve_rx_queue_stop_dqo,
> +       .tx_queue_stop        =3D gve_tx_queue_stop_dqo,
>         .link_update          =3D gve_link_update,
>         .stats_get            =3D gve_dev_stats_get,
>         .stats_reset          =3D gve_dev_stats_reset,
> @@ -877,12 +813,12 @@ gve_dev_init(struct rte_eth_dev *eth_dev)
>
>         if (gve_is_gqi(priv)) {
>                 eth_dev->dev_ops =3D &gve_eth_dev_ops;
> -               eth_dev->rx_pkt_burst =3D gve_rx_burst;
> -               eth_dev->tx_pkt_burst =3D gve_tx_burst;
> +               gve_set_rx_function(eth_dev);
> +               gve_set_tx_function(eth_dev);
>         } else {
>                 eth_dev->dev_ops =3D &gve_eth_dev_ops_dqo;
> -               eth_dev->rx_pkt_burst =3D gve_rx_burst_dqo;
> -               eth_dev->tx_pkt_burst =3D gve_tx_burst_dqo;
> +               gve_set_rx_function_dqo(eth_dev);
> +               gve_set_tx_function_dqo(eth_dev);
>         }
>
>         eth_dev->data->mac_addrs =3D &priv->dev_addr;
> diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h
> index 53a75044c5..cd62debd22 100644
> --- a/drivers/net/gve/gve_ethdev.h
> +++ b/drivers/net/gve/gve_ethdev.h
> @@ -367,6 +367,18 @@ gve_tx_queue_release(struct rte_eth_dev *dev,
> uint16_t qid);
>  void
>  gve_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
>
> +int
> +gve_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
> +
> +int
> +gve_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
> +
> +int
> +gve_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
> +
> +int
> +gve_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
> +
>  void
>  gve_stop_tx_queues(struct rte_eth_dev *dev);
>
> @@ -379,6 +391,12 @@ gve_rx_burst(void *rxq, struct rte_mbuf **rx_pkts,
> uint16_t nb_pkts);
>  uint16_t
>  gve_tx_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts);
>
> +void
> +gve_set_rx_function(struct rte_eth_dev *dev);
> +
> +void
> +gve_set_tx_function(struct rte_eth_dev *dev);
> +
>  /* Below functions are used for DQO */
>
>  int
> @@ -397,6 +415,18 @@ gve_tx_queue_release_dqo(struct rte_eth_dev *dev,
> uint16_t qid);
>  void
>  gve_rx_queue_release_dqo(struct rte_eth_dev *dev, uint16_t qid);
>
> +int
> +gve_rx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t rx_queue_id);
> +
> +int
> +gve_tx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t tx_queue_id);
> +
> +int
> +gve_rx_queue_stop_dqo(struct rte_eth_dev *dev, uint16_t rx_queue_id);
> +
> +int
> +gve_tx_queue_stop_dqo(struct rte_eth_dev *dev, uint16_t tx_queue_id);
> +
>  void
>  gve_stop_tx_queues_dqo(struct rte_eth_dev *dev);
>
> @@ -409,4 +439,10 @@ gve_rx_burst_dqo(void *rxq, struct rte_mbuf
> **rx_pkts, uint16_t nb_pkts);
>  uint16_t
>  gve_tx_burst_dqo(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)=
;
>
> +void
> +gve_set_rx_function_dqo(struct rte_eth_dev *dev);
> +
> +void
> +gve_set_tx_function_dqo(struct rte_eth_dev *dev);
> +
>  #endif /* _GVE_ETHDEV_H_ */
> diff --git a/drivers/net/gve/gve_rx.c b/drivers/net/gve/gve_rx.c
> index f2f6202404..b8c92ccda0 100644
> --- a/drivers/net/gve/gve_rx.c
> +++ b/drivers/net/gve/gve_rx.c
> @@ -414,11 +414,91 @@ gve_rx_queue_setup(struct rte_eth_dev *dev, uint16_=
t
> queue_id,
>         return err;
>  }
>
> +static int
> +gve_rxq_mbufs_alloc(struct gve_rx_queue *rxq)
> +{
> +       struct rte_mbuf *nmb;
> +       uint16_t i;
> +       int diag;
> +
> +       diag =3D rte_pktmbuf_alloc_bulk(rxq->mpool, &rxq->sw_ring[0],
> rxq->nb_rx_desc);
> +       if (diag < 0) {
> +               for (i =3D 0; i < rxq->nb_rx_desc - 1; i++) {
> +                       nmb =3D rte_pktmbuf_alloc(rxq->mpool);
> +                       if (!nmb)
> +                               break;
> +                       rxq->sw_ring[i] =3D nmb;
> +               }
> +               if (i < rxq->nb_rx_desc - 1)
> +                       return -ENOMEM;
> +       }
> +       rxq->nb_avail =3D 0;
> +       rxq->next_avail =3D rxq->nb_rx_desc - 1;
> +
> +       for (i =3D 0; i < rxq->nb_rx_desc; i++) {
> +               if (rxq->is_gqi_qpl) {
> +                       rxq->rx_data_ring[i].addr =3D rte_cpu_to_be_64(i =
*
> PAGE_SIZE);
> +               } else {
> +                       if (i =3D=3D rxq->nb_rx_desc - 1)
> +                               break;
> +                       nmb =3D rxq->sw_ring[i];
> +                       rxq->rx_data_ring[i].addr =3D
> rte_cpu_to_be_64(rte_mbuf_data_iova(nmb));
> +               }
> +       }
> +
> +       rte_write32(rte_cpu_to_be_32(rxq->next_avail), rxq->qrx_tail);
> +
> +       return 0;
> +}
> +
> +int
> +gve_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
> +{
> +       struct gve_priv *hw =3D dev->data->dev_private;
> +       struct gve_rx_queue *rxq;
> +       int ret;
> +
> +       if (rx_queue_id >=3D dev->data->nb_rx_queues)
> +               return -EINVAL;
> +
> +       rxq =3D dev->data->rx_queues[rx_queue_id];
> +
> +       rxq->qrx_tail =3D
> &hw->db_bar2[rte_be_to_cpu_32(rxq->qres->db_index)];
> +
> +       rte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), rxq->ntfy_addr);
> +
> +       ret =3D gve_rxq_mbufs_alloc(rxq);
> +       if (ret !=3D 0) {
> +               PMD_DRV_LOG(ERR, "Failed to alloc Rx queue mbuf");
> +               return ret;
> +       }
> +
> +       dev->data->rx_queue_state[rx_queue_id] =3D
> RTE_ETH_QUEUE_STATE_STARTED;
> +
> +       return 0;
> +}
> +
> +int
> +gve_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
> +{
> +       struct gve_rx_queue *rxq;
> +
> +       if (rx_queue_id >=3D dev->data->nb_rx_queues)
> +               return -EINVAL;
> +
> +       rxq =3D dev->data->rx_queues[rx_queue_id];
> +       gve_release_rxq_mbufs(rxq);
> +       gve_reset_rxq(rxq);
> +
> +       dev->data->rx_queue_state[rx_queue_id] =3D
> RTE_ETH_QUEUE_STATE_STOPPED;
> +
> +       return 0;
> +}
> +
>  void
>  gve_stop_rx_queues(struct rte_eth_dev *dev)
>  {
>         struct gve_priv *hw =3D dev->data->dev_private;
> -       struct gve_rx_queue *rxq;
>         uint16_t i;
>         int err;
>
> @@ -429,9 +509,13 @@ gve_stop_rx_queues(struct rte_eth_dev *dev)
>         if (err !=3D 0)
>                 PMD_DRV_LOG(WARNING, "failed to destroy rxqs");
>
> -       for (i =3D 0; i < dev->data->nb_rx_queues; i++) {
> -               rxq =3D dev->data->rx_queues[i];
> -               gve_release_rxq_mbufs(rxq);
> -               gve_reset_rxq(rxq);
> -       }
> +       for (i =3D 0; i < dev->data->nb_rx_queues; i++)
> +               if (gve_rx_queue_stop(dev, i) !=3D 0)
> +                       PMD_DRV_LOG(WARNING, "Fail to stop Rx queue %d",
> i);
> +}
> +
> +void
> +gve_set_rx_function(struct rte_eth_dev *dev)
> +{
> +       dev->rx_pkt_burst =3D gve_rx_burst;
>  }
> diff --git a/drivers/net/gve/gve_rx_dqo.c b/drivers/net/gve/gve_rx_dqo.c
> index 1d6b21359c..236aefd2a8 100644
> --- a/drivers/net/gve/gve_rx_dqo.c
> +++ b/drivers/net/gve/gve_rx_dqo.c
> @@ -333,11 +333,92 @@ gve_rx_queue_setup_dqo(struct rte_eth_dev *dev,
> uint16_t queue_id,
>         return err;
>  }
>
> +static int
> +gve_rxq_mbufs_alloc_dqo(struct gve_rx_queue *rxq)
> +{
> +       struct rte_mbuf *nmb;
> +       uint16_t i;
> +       int diag;
> +
> +       diag =3D rte_pktmbuf_alloc_bulk(rxq->mpool, &rxq->sw_ring[0],
> rxq->nb_rx_desc);
> +       if (diag < 0) {
> +               rxq->stats.no_mbufs_bulk++;
> +               for (i =3D 0; i < rxq->nb_rx_desc - 1; i++) {
> +                       nmb =3D rte_pktmbuf_alloc(rxq->mpool);
> +                       if (!nmb)
> +                               break;
> +                       rxq->sw_ring[i] =3D nmb;
> +               }
> +               if (i < rxq->nb_rx_desc - 1) {
> +                       rxq->stats.no_mbufs +=3D rxq->nb_rx_desc - 1 - i;
> +                       return -ENOMEM;
> +               }
> +       }
> +
> +       for (i =3D 0; i < rxq->nb_rx_desc; i++) {
> +               if (i =3D=3D rxq->nb_rx_desc - 1)
> +                       break;
> +               nmb =3D rxq->sw_ring[i];
> +               rxq->rx_ring[i].buf_addr =3D
> rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
> +               rxq->rx_ring[i].buf_id =3D rte_cpu_to_le_16(i);
> +       }
> +
> +       rxq->nb_rx_hold =3D 0;
> +       rxq->bufq_tail =3D rxq->nb_rx_desc - 1;
> +
> +       rte_write32(rxq->bufq_tail, rxq->qrx_tail);
> +
> +       return 0;
> +}
> +
> +int
> +gve_rx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t rx_queue_id)
> +{
> +       struct gve_priv *hw =3D dev->data->dev_private;
> +       struct gve_rx_queue *rxq;
> +       int ret;
> +
> +       if (rx_queue_id >=3D dev->data->nb_rx_queues)
> +               return -EINVAL;
> +
> +       rxq =3D dev->data->rx_queues[rx_queue_id];
> +
> +       rxq->qrx_tail =3D
> &hw->db_bar2[rte_be_to_cpu_32(rxq->qres->db_index)];
> +
> +       rte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), rxq->ntfy_addr);
> +
> +       ret =3D gve_rxq_mbufs_alloc_dqo(rxq);
> +       if (ret !=3D 0) {
> +               PMD_DRV_LOG(ERR, "Failed to alloc Rx queue mbuf");
> +               return ret;
> +       }
> +
> +       dev->data->rx_queue_state[rx_queue_id] =3D
> RTE_ETH_QUEUE_STATE_STARTED;
> +
> +       return 0;
> +}
> +
> +int
> +gve_rx_queue_stop_dqo(struct rte_eth_dev *dev, uint16_t rx_queue_id)
> +{
> +       struct gve_rx_queue *rxq;
> +
> +       if (rx_queue_id >=3D dev->data->nb_rx_queues)
> +               return -EINVAL;
> +
> +       rxq =3D dev->data->rx_queues[rx_queue_id];
> +       gve_release_rxq_mbufs_dqo(rxq);
> +       gve_reset_rxq_dqo(rxq);
> +
> +       dev->data->rx_queue_state[rx_queue_id] =3D
> RTE_ETH_QUEUE_STATE_STOPPED;
> +
> +       return 0;
> +}
> +
>  void
>  gve_stop_rx_queues_dqo(struct rte_eth_dev *dev)
>  {
>         struct gve_priv *hw =3D dev->data->dev_private;
> -       struct gve_rx_queue *rxq;
>         uint16_t i;
>         int err;
>
> @@ -345,9 +426,13 @@ gve_stop_rx_queues_dqo(struct rte_eth_dev *dev)
>         if (err !=3D 0)
>                 PMD_DRV_LOG(WARNING, "failed to destroy rxqs");
>
> -       for (i =3D 0; i < dev->data->nb_rx_queues; i++) {
> -               rxq =3D dev->data->rx_queues[i];
> -               gve_release_rxq_mbufs_dqo(rxq);
> -               gve_reset_rxq_dqo(rxq);
> -       }
> +       for (i =3D 0; i < dev->data->nb_rx_queues; i++)
> +               if (gve_rx_queue_stop_dqo(dev, i) !=3D 0)
> +                       PMD_DRV_LOG(WARNING, "Fail to stop Rx queue %d",
> i);
> +}
> +
> +void
> +gve_set_rx_function_dqo(struct rte_eth_dev *dev)
> +{
> +       dev->rx_pkt_burst =3D gve_rx_burst_dqo;
>  }
> diff --git a/drivers/net/gve/gve_tx.c b/drivers/net/gve/gve_tx.c
> index 13dc807623..2e0d001109 100644
> --- a/drivers/net/gve/gve_tx.c
> +++ b/drivers/net/gve/gve_tx.c
> @@ -664,11 +664,49 @@ gve_tx_queue_setup(struct rte_eth_dev *dev, uint16_=
t
> queue_id, uint16_t nb_desc,
>         return err;
>  }
>
> +int
> +gve_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
> +{
> +       struct gve_priv *hw =3D dev->data->dev_private;
> +       struct gve_tx_queue *txq;
> +
> +       if (tx_queue_id >=3D dev->data->nb_tx_queues)
> +               return -EINVAL;
> +
> +       txq =3D dev->data->tx_queues[tx_queue_id];
> +
> +       txq->qtx_tail =3D
> &hw->db_bar2[rte_be_to_cpu_32(txq->qres->db_index)];
> +       txq->qtx_head =3D
> +               &hw->cnt_array[rte_be_to_cpu_32(txq->qres->counter_index)=
];
> +
> +       rte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), txq->ntfy_addr);
> +
> +       dev->data->rx_queue_state[tx_queue_id] =3D
> RTE_ETH_QUEUE_STATE_STARTED;
> +
> +       return 0;
> +}
> +
> +int
> +gve_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
> +{
> +       struct gve_tx_queue *txq;
> +
> +       if (tx_queue_id >=3D dev->data->nb_tx_queues)
> +               return -EINVAL;
> +
> +       txq =3D dev->data->tx_queues[tx_queue_id];
> +       gve_release_txq_mbufs(txq);
> +       gve_reset_txq(txq);
> +
> +       dev->data->tx_queue_state[tx_queue_id] =3D
> RTE_ETH_QUEUE_STATE_STOPPED;
> +
> +       return 0;
> +}
> +
>  void
>  gve_stop_tx_queues(struct rte_eth_dev *dev)
>  {
>         struct gve_priv *hw =3D dev->data->dev_private;
> -       struct gve_tx_queue *txq;
>         uint16_t i;
>         int err;
>
> @@ -679,9 +717,13 @@ gve_stop_tx_queues(struct rte_eth_dev *dev)
>         if (err !=3D 0)
>                 PMD_DRV_LOG(WARNING, "failed to destroy txqs");
>
> -       for (i =3D 0; i < dev->data->nb_tx_queues; i++) {
> -               txq =3D dev->data->tx_queues[i];
> -               gve_release_txq_mbufs(txq);
> -               gve_reset_txq(txq);
> -       }
> +       for (i =3D 0; i < dev->data->nb_tx_queues; i++)
> +               if (gve_tx_queue_stop(dev, i) !=3D 0)
> +                       PMD_DRV_LOG(WARNING, "Fail to stop Tx queue %d",
> i);
> +}
> +
> +void
> +gve_set_tx_function(struct rte_eth_dev *dev)
> +{
> +       dev->tx_pkt_burst =3D gve_tx_burst;
>  }
> diff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c
> index b38eeaea4b..e0d144835b 100644
> --- a/drivers/net/gve/gve_tx_dqo.c
> +++ b/drivers/net/gve/gve_tx_dqo.c
> @@ -373,11 +373,49 @@ gve_tx_queue_setup_dqo(struct rte_eth_dev *dev,
> uint16_t queue_id,
>         return err;
>  }
>
> +int
> +gve_tx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t tx_queue_id)
> +{
> +       struct gve_priv *hw =3D dev->data->dev_private;
> +       struct gve_tx_queue *txq;
> +
> +       if (tx_queue_id >=3D dev->data->nb_tx_queues)
> +               return -EINVAL;
> +
> +       txq =3D dev->data->tx_queues[tx_queue_id];
> +
> +       txq->qtx_tail =3D
> &hw->db_bar2[rte_be_to_cpu_32(txq->qres->db_index)];
> +       txq->qtx_head =3D
> +               &hw->cnt_array[rte_be_to_cpu_32(txq->qres->counter_index)=
];
> +
> +       rte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), txq->ntfy_addr);
> +
> +       dev->data->rx_queue_state[tx_queue_id] =3D
> RTE_ETH_QUEUE_STATE_STARTED;
> +
> +       return 0;
> +}
> +
> +int
> +gve_tx_queue_stop_dqo(struct rte_eth_dev *dev, uint16_t tx_queue_id)
> +{
> +       struct gve_tx_queue *txq;
> +
> +       if (tx_queue_id >=3D dev->data->nb_tx_queues)
> +               return -EINVAL;
> +
> +       txq =3D dev->data->tx_queues[tx_queue_id];
> +       gve_release_txq_mbufs_dqo(txq);
> +       gve_reset_txq_dqo(txq);
> +
> +       dev->data->tx_queue_state[tx_queue_id] =3D
> RTE_ETH_QUEUE_STATE_STOPPED;
> +
> +       return 0;
> +}
> +
>  void
>  gve_stop_tx_queues_dqo(struct rte_eth_dev *dev)
>  {
>         struct gve_priv *hw =3D dev->data->dev_private;
> -       struct gve_tx_queue *txq;
>         uint16_t i;
>         int err;
>
> @@ -385,9 +423,13 @@ gve_stop_tx_queues_dqo(struct rte_eth_dev *dev)
>         if (err !=3D 0)
>                 PMD_DRV_LOG(WARNING, "failed to destroy txqs");
>
> -       for (i =3D 0; i < dev->data->nb_tx_queues; i++) {
> -               txq =3D dev->data->tx_queues[i];
> -               gve_release_txq_mbufs_dqo(txq);
> -               gve_reset_txq_dqo(txq);
> -       }
> +       for (i =3D 0; i < dev->data->nb_tx_queues; i++)
> +               if (gve_tx_queue_stop_dqo(dev, i) !=3D 0)
> +                       PMD_DRV_LOG(WARNING, "Fail to stop Tx queue %d",
> i);
> +}
> +
> +void
> +gve_set_tx_function_dqo(struct rte_eth_dev *dev)
> +{
> +       dev->tx_pkt_burst =3D gve_tx_burst_dqo;
>  }
> --
> 2.34.1
>
>

--0000000000003e049f05fbc14d6b
Content-Type: text/html; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

<div dir=3D"ltr"><div>tested-by: Rushil Gupta &lt;<a href=3D"mailto:rushilg=
@google.com" target=3D"_blank">rushilg@google.com</a>&gt;<br></div><br><div=
 class=3D"gmail_quote"><div dir=3D"ltr" class=3D"gmail_attr">On Mon, May 8,=
 2023 at 8:07=E2=80=AFPM Junfeng Guo &lt;<a href=3D"mailto:junfeng.guo@inte=
l.com" target=3D"_blank">junfeng.guo@intel.com</a>&gt; wrote:<br></div><blo=
ckquote class=3D"gmail_quote" style=3D"margin:0px 0px 0px 0.8ex;border-left=
:1px solid rgb(204,204,204);padding-left:1ex">Add support for queue operati=
ons for GQI:<br>
=C2=A0- gve_rx_queue_start<br>
=C2=A0- gve_tx_queue_start<br>
=C2=A0- gve_rx_queue_stop<br>
=C2=A0- gve_tx_queue_stop<br>
<br>
Add support for queue operations for DQO:<br>
=C2=A0- gve_rx_queue_start_dqo<br>
=C2=A0- gve_tx_queue_start_dqo<br>
=C2=A0- gve_rx_queue_stop_dqo<br>
=C2=A0- gve_tx_queue_stop_dqo<br>
<br>
Also move the funcs of rxq_mbufs_alloc into the corresponding files.<br>
<br>
Signed-off-by: Junfeng Guo &lt;<a href=3D"mailto:junfeng.guo@intel.com" tar=
get=3D"_blank">junfeng.guo@intel.com</a>&gt;<br>
---<br>
=C2=A0drivers/net/gve/gve_ethdev.c | 166 +++++++++++-----------------------=
-<br>
=C2=A0drivers/net/gve/gve_ethdev.h |=C2=A0 36 ++++++++<br>
=C2=A0drivers/net/gve/gve_rx.c=C2=A0 =C2=A0 =C2=A0|=C2=A0 96 ++++++++++++++=
++++--<br>
=C2=A0drivers/net/gve/gve_rx_dqo.c |=C2=A0 97 ++++++++++++++++++--<br>
=C2=A0drivers/net/gve/gve_tx.c=C2=A0 =C2=A0 =C2=A0|=C2=A0 54 ++++++++++--<b=
r>
=C2=A0drivers/net/gve/gve_tx_dqo.c |=C2=A0 54 ++++++++++--<br>
=C2=A06 files changed, 364 insertions(+), 139 deletions(-)<br>
<br>
diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c<br=
>
index 8b6861a24f..1dcb3b3a01 100644<br>
--- a/drivers/net/gve/gve_ethdev.c<br>
+++ b/drivers/net/gve/gve_ethdev.c<br>
@@ -104,81 +104,6 @@ gve_dev_configure(struct rte_eth_dev *dev)<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0;<br>
=C2=A0}<br>
<br>
-static int<br>
-gve_refill_pages(struct gve_rx_queue *rxq)<br>
-{<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0struct rte_mbuf *nmb;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0uint16_t i;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0int diag;<br>
-<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0diag =3D rte_pktmbuf_alloc_bulk(rxq-&gt;mpool, =
&amp;rxq-&gt;sw_ring[0], rxq-&gt;nb_rx_desc);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0if (diag &lt; 0) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt=
; rxq-&gt;nb_rx_desc - 1; i++) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0nmb =3D rte_pktmbuf_alloc(rxq-&gt;mpool);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0if (!nmb)<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0rxq-&gt;sw_ring[i] =3D nmb;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (i &lt; rxq-&gt;=
nb_rx_desc - 1)<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0return -ENOMEM;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;nb_avail =3D 0;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;next_avail =3D rxq-&gt;nb_rx_desc - 1;<=
br>
-<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt; rxq-&gt;nb_rx_desc; i++) {=
<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (rxq-&gt;is_gqi_=
qpl) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0rxq-&gt;rx_data_ring[i].addr =3D rte_cpu_to_be_64(i * PAGE_SIZE);=
<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0if (i =3D=3D rxq-&gt;nb_rx_desc - 1)<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0nmb =3D rxq-&gt;sw_ring[i];<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0rxq-&gt;rx_data_ring[i].addr =3D rte_cpu_to_be_64(rte_mbuf_data_i=
ova(nmb));<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
-<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0rte_write32(rte_cpu_to_be_32(rxq-&gt;next_avail=
), rxq-&gt;qrx_tail);<br>
-<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;<br>
-}<br>
-<br>
-static int<br>
-gve_refill_dqo(struct gve_rx_queue *rxq)<br>
-{<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0struct rte_mbuf *nmb;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0uint16_t i;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0int diag;<br>
-<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0diag =3D rte_pktmbuf_alloc_bulk(rxq-&gt;mpool, =
&amp;rxq-&gt;sw_ring[0], rxq-&gt;nb_rx_desc);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0if (diag &lt; 0) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;stats.no_mb=
ufs_bulk++;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt=
; rxq-&gt;nb_rx_desc - 1; i++) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0nmb =3D rte_pktmbuf_alloc(rxq-&gt;mpool);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0if (!nmb)<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0rxq-&gt;sw_ring[i] =3D nmb;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (i &lt; rxq-&gt;=
nb_rx_desc - 1) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0rxq-&gt;stats.no_mbufs +=3D rxq-&gt;nb_rx_desc - 1 - i;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0return -ENOMEM;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
-<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt; rxq-&gt;nb_rx_desc; i++) {=
<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (i =3D=3D rxq-&g=
t;nb_rx_desc - 1)<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0break;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0nmb =3D rxq-&gt;sw_=
ring[i];<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;rx_ring[i].=
buf_addr =3D rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;rx_ring[i].=
buf_id =3D rte_cpu_to_le_16(i);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
-<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;nb_rx_hold =3D 0;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;bufq_tail =3D rxq-&gt;nb_rx_desc - 1;<b=
r>
-<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0rte_write32(rxq-&gt;bufq_tail, rxq-&gt;qrx_tail=
);<br>
-<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;<br>
-}<br>
-<br>
=C2=A0static int<br>
=C2=A0gve_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_com=
plete)<br>
=C2=A0{<br>
@@ -208,65 +133,68 @@ gve_link_update(struct rte_eth_dev *dev, __rte_unused=
 int wait_to_complete)<br>
=C2=A0}<br>
<br>
=C2=A0static int<br>
-gve_dev_start(struct rte_eth_dev *dev)<br>
+gve_start_queues(struct rte_eth_dev *dev)<br>
=C2=A0{<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0uint16_t num_queues =3D dev-&gt;data-&gt;nb_tx_=
queues;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 struct gve_priv *priv =3D dev-&gt;data-&gt;dev_=
private;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_tx_queue *txq;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_rx_queue *rxq;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0uint16_t num_queues;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 uint16_t i;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0int err;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0int ret;<br>
<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0num_queues =3D dev-&gt;data-&gt;nb_tx_queues;<b=
r>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 priv-&gt;txqs =3D (struct gve_tx_queue **)dev-&=
gt;data-&gt;tx_queues;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0err =3D gve_adminq_create_tx_queues(priv, num_q=
ueues);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0if (err) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0PMD_DRV_LOG(ERR, &q=
uot;failed to create %u tx queues.&quot;, num_queues);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return err;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt; num_queues; i++) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0txq =3D priv-&gt;tx=
qs[i];<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0txq-&gt;qtx_tail =
=3D<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&amp;priv-&gt;db_ba=
r2[rte_be_to_cpu_32(txq-&gt;qres-&gt;db_index)];<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0txq-&gt;qtx_head =
=3D<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&amp;priv-&gt;cnt_a=
rray[rte_be_to_cpu_32(txq-&gt;qres-&gt;counter_index)];<br>
-<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rte_write32(rte_cpu=
_to_be_32(GVE_IRQ_MASK), txq-&gt;ntfy_addr);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D gve_adminq_create_tx_queues(priv, num_q=
ueues);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (ret !=3D 0) {<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0PMD_DRV_LOG(ERR, &q=
uot;Failed to create %u tx queues.&quot;, num_queues);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return ret;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt; num_queues; i++)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (gve_tx_queue_st=
art(dev, i) !=3D 0) {<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0PMD_DRV_LOG(ERR, &quot;Fail to start Tx queue %d&quot;, i);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0goto err_tx;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 num_queues =3D dev-&gt;data-&gt;nb_rx_queues;<b=
r>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 priv-&gt;rxqs =3D (struct gve_rx_queue **)dev-&=
gt;data-&gt;rx_queues;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0err =3D gve_adminq_create_rx_queues(priv, num_q=
ueues);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0if (err) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0PMD_DRV_LOG(ERR, &q=
uot;failed to create %u rx queues.&quot;, num_queues);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D gve_adminq_create_rx_queues(priv, num_q=
ueues);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (ret !=3D 0) {<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0PMD_DRV_LOG(ERR, &q=
uot;Failed to create %u rx queues.&quot;, num_queues);<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto err_tx;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 }<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 for (i =3D 0; i &lt; num_queues; i++) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rxq =3D priv-&gt;rx=
qs[i];<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;qrx_tail =
=3D<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&amp;priv-&gt;db_ba=
r2[rte_be_to_cpu_32(rxq-&gt;qres-&gt;db_index)];<br>
-<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rte_write32(rte_cpu=
_to_be_32(GVE_IRQ_MASK), rxq-&gt;ntfy_addr);<br>
-<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (gve_is_gqi(priv=
))<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0err =3D gve_refill_pages(rxq);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0ret =3D gve_rx_queue_start(dev, i);<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 else<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0err =3D gve_refill_dqo(rxq);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (err) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0PMD_DRV_LOG(ERR, &quot;Failed to refill for RX&quot;);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0ret =3D gve_rx_queue_start_dqo(dev, i);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (ret !=3D 0) {<b=
r>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0PMD_DRV_LOG(ERR, &quot;Fail to start Rx queue %d&quot;, i);<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 goto err_rx;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 }<br>
<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0dev-&gt;data-&gt;dev_started =3D 1;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0gve_link_update(dev, 0);<br>
-<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0;<br>
<br>
=C2=A0err_rx:<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 gve_stop_rx_queues(dev);<br>
=C2=A0err_tx:<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 gve_stop_tx_queues(dev);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0return err;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return ret;<br>
+}<br>
+<br>
+static int<br>
+gve_dev_start(struct rte_eth_dev *dev)<br>
+{<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0int ret;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D gve_start_queues(dev);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (ret !=3D 0) {<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0PMD_DRV_LOG(ERR, &q=
uot;Failed to start queues&quot;);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return ret;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0dev-&gt;data-&gt;dev_started =3D 1;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0gve_link_update(dev, 0);<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;<br>
=C2=A0}<br>
<br>
=C2=A0static int<br>
@@ -573,6 +501,10 @@ static const struct eth_dev_ops gve_eth_dev_ops =3D {<=
br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 .tx_queue_setup=C2=A0 =C2=A0 =C2=A0 =C2=A0=3D g=
ve_tx_queue_setup,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 .rx_queue_release=C2=A0 =C2=A0 =C2=A0=3D gve_rx=
_queue_release,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 .tx_queue_release=C2=A0 =C2=A0 =C2=A0=3D gve_tx=
_queue_release,<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0.rx_queue_start=C2=A0 =C2=A0 =C2=A0 =C2=A0=3D g=
ve_rx_queue_start,<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0.tx_queue_start=C2=A0 =C2=A0 =C2=A0 =C2=A0=3D g=
ve_tx_queue_start,<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0.rx_queue_stop=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D g=
ve_rx_queue_stop,<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0.tx_queue_stop=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D g=
ve_tx_queue_stop,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 .link_update=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=3D gve_link_update,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 .stats_get=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =3D gve_dev_stats_get,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 .stats_reset=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=3D gve_dev_stats_reset,<br>
@@ -591,6 +523,10 @@ static const struct eth_dev_ops gve_eth_dev_ops_dqo =
=3D {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 .tx_queue_setup=C2=A0 =C2=A0 =C2=A0 =C2=A0=3D g=
ve_tx_queue_setup_dqo,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 .rx_queue_release=C2=A0 =C2=A0 =C2=A0=3D gve_rx=
_queue_release_dqo,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 .tx_queue_release=C2=A0 =C2=A0 =C2=A0=3D gve_tx=
_queue_release_dqo,<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0.rx_queue_start=C2=A0 =C2=A0 =C2=A0 =C2=A0=3D g=
ve_rx_queue_start_dqo,<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0.tx_queue_start=C2=A0 =C2=A0 =C2=A0 =C2=A0=3D g=
ve_tx_queue_start_dqo,<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0.rx_queue_stop=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D g=
ve_rx_queue_stop_dqo,<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0.tx_queue_stop=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D g=
ve_tx_queue_stop_dqo,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 .link_update=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=3D gve_link_update,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 .stats_get=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =3D gve_dev_stats_get,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 .stats_reset=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=3D gve_dev_stats_reset,<br>
@@ -877,12 +813,12 @@ gve_dev_init(struct rte_eth_dev *eth_dev)<br>
<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (gve_is_gqi(priv)) {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 eth_dev-&gt;dev_ops=
 =3D &amp;gve_eth_dev_ops;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0eth_dev-&gt;rx_pkt_=
burst =3D gve_rx_burst;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0eth_dev-&gt;tx_pkt_=
burst =3D gve_tx_burst;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gve_set_rx_function=
(eth_dev);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gve_set_tx_function=
(eth_dev);<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 eth_dev-&gt;dev_ops=
 =3D &amp;gve_eth_dev_ops_dqo;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0eth_dev-&gt;rx_pkt_=
burst =3D gve_rx_burst_dqo;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0eth_dev-&gt;tx_pkt_=
burst =3D gve_tx_burst_dqo;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gve_set_rx_function=
_dqo(eth_dev);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gve_set_tx_function=
_dqo(eth_dev);<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 }<br>
<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 eth_dev-&gt;data-&gt;mac_addrs =3D &amp;priv-&g=
t;dev_addr;<br>
diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h<br=
>
index 53a75044c5..cd62debd22 100644<br>
--- a/drivers/net/gve/gve_ethdev.h<br>
+++ b/drivers/net/gve/gve_ethdev.h<br>
@@ -367,6 +367,18 @@ gve_tx_queue_release(struct rte_eth_dev *dev, uint16_t=
 qid);<br>
=C2=A0void<br>
=C2=A0gve_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);<br>
<br>
+int<br>
+gve_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);<br>
+<br>
+int<br>
+gve_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);<br>
+<br>
+int<br>
+gve_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);<br>
+<br>
+int<br>
+gve_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);<br>
+<br>
=C2=A0void<br>
=C2=A0gve_stop_tx_queues(struct rte_eth_dev *dev);<br>
<br>
@@ -379,6 +391,12 @@ gve_rx_burst(void *rxq, struct rte_mbuf **rx_pkts, uin=
t16_t nb_pkts);<br>
=C2=A0uint16_t<br>
=C2=A0gve_tx_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts);=
<br>
<br>
+void<br>
+gve_set_rx_function(struct rte_eth_dev *dev);<br>
+<br>
+void<br>
+gve_set_tx_function(struct rte_eth_dev *dev);<br>
+<br>
=C2=A0/* Below functions are used for DQO */<br>
<br>
=C2=A0int<br>
@@ -397,6 +415,18 @@ gve_tx_queue_release_dqo(struct rte_eth_dev *dev, uint=
16_t qid);<br>
=C2=A0void<br>
=C2=A0gve_rx_queue_release_dqo(struct rte_eth_dev *dev, uint16_t qid);<br>
<br>
+int<br>
+gve_rx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t rx_queue_id);<br>
+<br>
+int<br>
+gve_tx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t tx_queue_id);<br>
+<br>
+int<br>
+gve_rx_queue_stop_dqo(struct rte_eth_dev *dev, uint16_t rx_queue_id);<br>
+<br>
+int<br>
+gve_tx_queue_stop_dqo(struct rte_eth_dev *dev, uint16_t tx_queue_id);<br>
+<br>
=C2=A0void<br>
=C2=A0gve_stop_tx_queues_dqo(struct rte_eth_dev *dev);<br>
<br>
@@ -409,4 +439,10 @@ gve_rx_burst_dqo(void *rxq, struct rte_mbuf **rx_pkts,=
 uint16_t nb_pkts);<br>
=C2=A0uint16_t<br>
=C2=A0gve_tx_burst_dqo(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pk=
ts);<br>
<br>
+void<br>
+gve_set_rx_function_dqo(struct rte_eth_dev *dev);<br>
+<br>
+void<br>
+gve_set_tx_function_dqo(struct rte_eth_dev *dev);<br>
+<br>
=C2=A0#endif /* _GVE_ETHDEV_H_ */<br>
diff --git a/drivers/net/gve/gve_rx.c b/drivers/net/gve/gve_rx.c<br>
index f2f6202404..b8c92ccda0 100644<br>
--- a/drivers/net/gve/gve_rx.c<br>
+++ b/drivers/net/gve/gve_rx.c<br>
@@ -414,11 +414,91 @@ gve_rx_queue_setup(struct rte_eth_dev *dev, uint16_t =
queue_id,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 return err;<br>
=C2=A0}<br>
<br>
+static int<br>
+gve_rxq_mbufs_alloc(struct gve_rx_queue *rxq)<br>
+{<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct rte_mbuf *nmb;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0uint16_t i;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0int diag;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0diag =3D rte_pktmbuf_alloc_bulk(rxq-&gt;mpool, =
&amp;rxq-&gt;sw_ring[0], rxq-&gt;nb_rx_desc);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (diag &lt; 0) {<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt=
; rxq-&gt;nb_rx_desc - 1; i++) {<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0nmb =3D rte_pktmbuf_alloc(rxq-&gt;mpool);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0if (!nmb)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0rxq-&gt;sw_ring[i] =3D nmb;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (i &lt; rxq-&gt;=
nb_rx_desc - 1)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0return -ENOMEM;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;nb_avail =3D 0;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;next_avail =3D rxq-&gt;nb_rx_desc - 1;<=
br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt; rxq-&gt;nb_rx_desc; i++) {=
<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (rxq-&gt;is_gqi_=
qpl) {<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0rxq-&gt;rx_data_ring[i].addr =3D rte_cpu_to_be_64(i * PAGE_SIZE);=
<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else {<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0if (i =3D=3D rxq-&gt;nb_rx_desc - 1)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0nmb =3D rxq-&gt;sw_ring[i];<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0rxq-&gt;rx_data_ring[i].addr =3D rte_cpu_to_be_64(rte_mbuf_data_i=
ova(nmb));<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rte_write32(rte_cpu_to_be_32(rxq-&gt;next_avail=
), rxq-&gt;qrx_tail);<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;<br>
+}<br>
+<br>
+int<br>
+gve_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)<br>
+{<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_priv *hw =3D dev-&gt;data-&gt;dev_pr=
ivate;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_rx_queue *rxq;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0int ret;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (rx_queue_id &gt;=3D dev-&gt;data-&gt;nb_rx_=
queues)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return -EINVAL;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rxq =3D dev-&gt;data-&gt;rx_queues[rx_queue_id]=
;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;qrx_tail =3D &amp;hw-&gt;db_bar2[rte_be=
_to_cpu_32(rxq-&gt;qres-&gt;db_index)];<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), rxq=
-&gt;ntfy_addr);<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D gve_rxq_mbufs_alloc(rxq);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (ret !=3D 0) {<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0PMD_DRV_LOG(ERR, &q=
uot;Failed to alloc Rx queue mbuf&quot;);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return ret;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0dev-&gt;data-&gt;rx_queue_state[rx_queue_id] =
=3D RTE_ETH_QUEUE_STATE_STARTED;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;<br>
+}<br>
+<br>
+int<br>
+gve_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)<br>
+{<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_rx_queue *rxq;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (rx_queue_id &gt;=3D dev-&gt;data-&gt;nb_rx_=
queues)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return -EINVAL;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rxq =3D dev-&gt;data-&gt;rx_queues[rx_queue_id]=
;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0gve_release_rxq_mbufs(rxq);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0gve_reset_rxq(rxq);<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0dev-&gt;data-&gt;rx_queue_state[rx_queue_id] =
=3D RTE_ETH_QUEUE_STATE_STOPPED;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;<br>
+}<br>
+<br>
=C2=A0void<br>
=C2=A0gve_stop_rx_queues(struct rte_eth_dev *dev)<br>
=C2=A0{<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 struct gve_priv *hw =3D dev-&gt;data-&gt;dev_pr=
ivate;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_rx_queue *rxq;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 uint16_t i;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 int err;<br>
<br>
@@ -429,9 +509,13 @@ gve_stop_rx_queues(struct rte_eth_dev *dev)<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (err !=3D 0)<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PMD_DRV_LOG(WARNING=
, &quot;failed to destroy rxqs&quot;);<br>
<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt; dev-&gt;data-&gt;nb_rx_que=
ues; i++) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rxq =3D dev-&gt;dat=
a-&gt;rx_queues[i];<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gve_release_rxq_mbu=
fs(rxq);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gve_reset_rxq(rxq);=
<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt; dev-&gt;data-&gt;nb_rx_que=
ues; i++)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (gve_rx_queue_st=
op(dev, i) !=3D 0)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0PMD_DRV_LOG(WARNING, &quot;Fail to stop Rx queue %d&quot;, i);<br=
>
+}<br>
+<br>
+void<br>
+gve_set_rx_function(struct rte_eth_dev *dev)<br>
+{<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0dev-&gt;rx_pkt_burst =3D gve_rx_burst;<br>
=C2=A0}<br>
diff --git a/drivers/net/gve/gve_rx_dqo.c b/drivers/net/gve/gve_rx_dqo.c<br=
>
index 1d6b21359c..236aefd2a8 100644<br>
--- a/drivers/net/gve/gve_rx_dqo.c<br>
+++ b/drivers/net/gve/gve_rx_dqo.c<br>
@@ -333,11 +333,92 @@ gve_rx_queue_setup_dqo(struct rte_eth_dev *dev, uint1=
6_t queue_id,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 return err;<br>
=C2=A0}<br>
<br>
+static int<br>
+gve_rxq_mbufs_alloc_dqo(struct gve_rx_queue *rxq)<br>
+{<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct rte_mbuf *nmb;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0uint16_t i;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0int diag;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0diag =3D rte_pktmbuf_alloc_bulk(rxq-&gt;mpool, =
&amp;rxq-&gt;sw_ring[0], rxq-&gt;nb_rx_desc);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (diag &lt; 0) {<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;stats.no_mb=
ufs_bulk++;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt=
; rxq-&gt;nb_rx_desc - 1; i++) {<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0nmb =3D rte_pktmbuf_alloc(rxq-&gt;mpool);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0if (!nmb)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0rxq-&gt;sw_ring[i] =3D nmb;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (i &lt; rxq-&gt;=
nb_rx_desc - 1) {<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0rxq-&gt;stats.no_mbufs +=3D rxq-&gt;nb_rx_desc - 1 - i;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0return -ENOMEM;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt; rxq-&gt;nb_rx_desc; i++) {=
<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (i =3D=3D rxq-&g=
t;nb_rx_desc - 1)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0break;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0nmb =3D rxq-&gt;sw_=
ring[i];<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;rx_ring[i].=
buf_addr =3D rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;rx_ring[i].=
buf_id =3D rte_cpu_to_le_16(i);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;nb_rx_hold =3D 0;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;bufq_tail =3D rxq-&gt;nb_rx_desc - 1;<b=
r>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rte_write32(rxq-&gt;bufq_tail, rxq-&gt;qrx_tail=
);<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;<br>
+}<br>
+<br>
+int<br>
+gve_rx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t rx_queue_id)<br>
+{<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_priv *hw =3D dev-&gt;data-&gt;dev_pr=
ivate;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_rx_queue *rxq;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0int ret;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (rx_queue_id &gt;=3D dev-&gt;data-&gt;nb_rx_=
queues)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return -EINVAL;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rxq =3D dev-&gt;data-&gt;rx_queues[rx_queue_id]=
;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rxq-&gt;qrx_tail =3D &amp;hw-&gt;db_bar2[rte_be=
_to_cpu_32(rxq-&gt;qres-&gt;db_index)];<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), rxq=
-&gt;ntfy_addr);<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D gve_rxq_mbufs_alloc_dqo(rxq);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (ret !=3D 0) {<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0PMD_DRV_LOG(ERR, &q=
uot;Failed to alloc Rx queue mbuf&quot;);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return ret;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0dev-&gt;data-&gt;rx_queue_state[rx_queue_id] =
=3D RTE_ETH_QUEUE_STATE_STARTED;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;<br>
+}<br>
+<br>
+int<br>
+gve_rx_queue_stop_dqo(struct rte_eth_dev *dev, uint16_t rx_queue_id)<br>
+{<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_rx_queue *rxq;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (rx_queue_id &gt;=3D dev-&gt;data-&gt;nb_rx_=
queues)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return -EINVAL;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rxq =3D dev-&gt;data-&gt;rx_queues[rx_queue_id]=
;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0gve_release_rxq_mbufs_dqo(rxq);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0gve_reset_rxq_dqo(rxq);<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0dev-&gt;data-&gt;rx_queue_state[rx_queue_id] =
=3D RTE_ETH_QUEUE_STATE_STOPPED;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;<br>
+}<br>
+<br>
=C2=A0void<br>
=C2=A0gve_stop_rx_queues_dqo(struct rte_eth_dev *dev)<br>
=C2=A0{<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 struct gve_priv *hw =3D dev-&gt;data-&gt;dev_pr=
ivate;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_rx_queue *rxq;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 uint16_t i;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 int err;<br>
<br>
@@ -345,9 +426,13 @@ gve_stop_rx_queues_dqo(struct rte_eth_dev *dev)<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (err !=3D 0)<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PMD_DRV_LOG(WARNING=
, &quot;failed to destroy rxqs&quot;);<br>
<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt; dev-&gt;data-&gt;nb_rx_que=
ues; i++) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rxq =3D dev-&gt;dat=
a-&gt;rx_queues[i];<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gve_release_rxq_mbu=
fs_dqo(rxq);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gve_reset_rxq_dqo(r=
xq);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt; dev-&gt;data-&gt;nb_rx_que=
ues; i++)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (gve_rx_queue_st=
op_dqo(dev, i) !=3D 0)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0PMD_DRV_LOG(WARNING, &quot;Fail to stop Rx queue %d&quot;, i);<br=
>
+}<br>
+<br>
+void<br>
+gve_set_rx_function_dqo(struct rte_eth_dev *dev)<br>
+{<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0dev-&gt;rx_pkt_burst =3D gve_rx_burst_dqo;<br>
=C2=A0}<br>
diff --git a/drivers/net/gve/gve_tx.c b/drivers/net/gve/gve_tx.c<br>
index 13dc807623..2e0d001109 100644<br>
--- a/drivers/net/gve/gve_tx.c<br>
+++ b/drivers/net/gve/gve_tx.c<br>
@@ -664,11 +664,49 @@ gve_tx_queue_setup(struct rte_eth_dev *dev, uint16_t =
queue_id, uint16_t nb_desc,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 return err;<br>
=C2=A0}<br>
<br>
+int<br>
+gve_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)<br>
+{<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_priv *hw =3D dev-&gt;data-&gt;dev_pr=
ivate;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_tx_queue *txq;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (tx_queue_id &gt;=3D dev-&gt;data-&gt;nb_tx_=
queues)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return -EINVAL;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0txq =3D dev-&gt;data-&gt;tx_queues[tx_queue_id]=
;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0txq-&gt;qtx_tail =3D &amp;hw-&gt;db_bar2[rte_be=
_to_cpu_32(txq-&gt;qres-&gt;db_index)];<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0txq-&gt;qtx_head =3D<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&amp;hw-&gt;cnt_arr=
ay[rte_be_to_cpu_32(txq-&gt;qres-&gt;counter_index)];<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), txq=
-&gt;ntfy_addr);<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0dev-&gt;data-&gt;rx_queue_state[tx_queue_id] =
=3D RTE_ETH_QUEUE_STATE_STARTED;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;<br>
+}<br>
+<br>
+int<br>
+gve_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)<br>
+{<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_tx_queue *txq;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (tx_queue_id &gt;=3D dev-&gt;data-&gt;nb_tx_=
queues)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return -EINVAL;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0txq =3D dev-&gt;data-&gt;tx_queues[tx_queue_id]=
;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0gve_release_txq_mbufs(txq);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0gve_reset_txq(txq);<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0dev-&gt;data-&gt;tx_queue_state[tx_queue_id] =
=3D RTE_ETH_QUEUE_STATE_STOPPED;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;<br>
+}<br>
+<br>
=C2=A0void<br>
=C2=A0gve_stop_tx_queues(struct rte_eth_dev *dev)<br>
=C2=A0{<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 struct gve_priv *hw =3D dev-&gt;data-&gt;dev_pr=
ivate;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_tx_queue *txq;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 uint16_t i;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 int err;<br>
<br>
@@ -679,9 +717,13 @@ gve_stop_tx_queues(struct rte_eth_dev *dev)<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (err !=3D 0)<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PMD_DRV_LOG(WARNING=
, &quot;failed to destroy txqs&quot;);<br>
<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt; dev-&gt;data-&gt;nb_tx_que=
ues; i++) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0txq =3D dev-&gt;dat=
a-&gt;tx_queues[i];<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gve_release_txq_mbu=
fs(txq);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gve_reset_txq(txq);=
<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt; dev-&gt;data-&gt;nb_tx_que=
ues; i++)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (gve_tx_queue_st=
op(dev, i) !=3D 0)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0PMD_DRV_LOG(WARNING, &quot;Fail to stop Tx queue %d&quot;, i);<br=
>
+}<br>
+<br>
+void<br>
+gve_set_tx_function(struct rte_eth_dev *dev)<br>
+{<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0dev-&gt;tx_pkt_burst =3D gve_tx_burst;<br>
=C2=A0}<br>
diff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c<br=
>
index b38eeaea4b..e0d144835b 100644<br>
--- a/drivers/net/gve/gve_tx_dqo.c<br>
+++ b/drivers/net/gve/gve_tx_dqo.c<br>
@@ -373,11 +373,49 @@ gve_tx_queue_setup_dqo(struct rte_eth_dev *dev, uint1=
6_t queue_id,<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 return err;<br>
=C2=A0}<br>
<br>
+int<br>
+gve_tx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t tx_queue_id)<br>
+{<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_priv *hw =3D dev-&gt;data-&gt;dev_pr=
ivate;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_tx_queue *txq;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (tx_queue_id &gt;=3D dev-&gt;data-&gt;nb_tx_=
queues)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return -EINVAL;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0txq =3D dev-&gt;data-&gt;tx_queues[tx_queue_id]=
;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0txq-&gt;qtx_tail =3D &amp;hw-&gt;db_bar2[rte_be=
_to_cpu_32(txq-&gt;qres-&gt;db_index)];<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0txq-&gt;qtx_head =3D<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&amp;hw-&gt;cnt_arr=
ay[rte_be_to_cpu_32(txq-&gt;qres-&gt;counter_index)];<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), txq=
-&gt;ntfy_addr);<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0dev-&gt;data-&gt;rx_queue_state[tx_queue_id] =
=3D RTE_ETH_QUEUE_STATE_STARTED;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;<br>
+}<br>
+<br>
+int<br>
+gve_tx_queue_stop_dqo(struct rte_eth_dev *dev, uint16_t tx_queue_id)<br>
+{<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_tx_queue *txq;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (tx_queue_id &gt;=3D dev-&gt;data-&gt;nb_tx_=
queues)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return -EINVAL;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0txq =3D dev-&gt;data-&gt;tx_queues[tx_queue_id]=
;<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0gve_release_txq_mbufs_dqo(txq);<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0gve_reset_txq_dqo(txq);<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0dev-&gt;data-&gt;tx_queue_state[tx_queue_id] =
=3D RTE_ETH_QUEUE_STATE_STOPPED;<br>
+<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;<br>
+}<br>
+<br>
=C2=A0void<br>
=C2=A0gve_stop_tx_queues_dqo(struct rte_eth_dev *dev)<br>
=C2=A0{<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 struct gve_priv *hw =3D dev-&gt;data-&gt;dev_pr=
ivate;<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0struct gve_tx_queue *txq;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 uint16_t i;<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 int err;<br>
<br>
@@ -385,9 +423,13 @@ gve_stop_tx_queues_dqo(struct rte_eth_dev *dev)<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (err !=3D 0)<br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PMD_DRV_LOG(WARNING=
, &quot;failed to destroy txqs&quot;);<br>
<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt; dev-&gt;data-&gt;nb_tx_que=
ues; i++) {<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0txq =3D dev-&gt;dat=
a-&gt;tx_queues[i];<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gve_release_txq_mbu=
fs_dqo(txq);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gve_reset_txq_dqo(t=
xq);<br>
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i &lt; dev-&gt;data-&gt;nb_tx_que=
ues; i++)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (gve_tx_queue_st=
op_dqo(dev, i) !=3D 0)<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0PMD_DRV_LOG(WARNING, &quot;Fail to stop Tx queue %d&quot;, i);<br=
>
+}<br>
+<br>
+void<br>
+gve_set_tx_function_dqo(struct rte_eth_dev *dev)<br>
+{<br>
+=C2=A0 =C2=A0 =C2=A0 =C2=A0dev-&gt;tx_pkt_burst =3D gve_tx_burst_dqo;<br>
=C2=A0}<br>
-- <br>
2.34.1<br>
<br>
</blockquote></div></div>

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