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From: Manish Sharma <manish.sharmajee75@gmail.com>
To: dev@dpdk.org
Subject: [dpdk-dev] rte_memcpy - fence and stream
Date: Mon, 24 May 2021 23:43:24 +0530	[thread overview]
Message-ID: <CAOT2AHX7Zf-N-wFRJePSHfaup2ogxR6udNeT82zxjOSH5n0xpw@mail.gmail.com> (raw)
In-Reply-To: <CAOT2AHVSfmYi3rB4cnXwi-NDf7hG8_p97G5FLnD0-PxaL637MA@mail.gmail.com>

I am looking at the source for rte_memcpy (this is a discussion only for
x86-64)

For one of the cases, when aligned correctly, it uses

/**
 * Copy 64 bytes from one location to another,
 * locations should not overlap.
 */
static __rte_always_inline void
rte_mov64(uint8_t *dst, const uint8_t *src)
{
        __m512i zmm0;

        zmm0 = _mm512_loadu_si512((const void *)src);
        _mm512_storeu_si512((void *)dst, zmm0);
}

I had some questions about this:

1. What I dont see is any use of x86 fence(rmb,wmb) instructions. Is that
not required in this case and if not, why isnt it needed?

2. Are the  mm512_loadu_si512 and  _mm512_storeu_si512 non temporal?

3. Why isn't the code using  stream variants, _mm512_stream_load_si512 and
friends? It would not pollute the cache, so should be better - unless the
required fence instructions cause a drop in performance?

4. Do the _mm512_stream_load_si512 need fence instructions? Based on my
reading of the spec, the answer is yes - but wanted to confirm.

TIA,
Manish

  reply	other threads:[~2021-05-24 18:13 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-24  8:49 [dpdk-dev] rte_memcpy Manish Sharma
2021-05-24 18:13 ` Manish Sharma [this message]
2021-05-25  9:20   ` [dpdk-dev] rte_memcpy - fence and stream Bruce Richardson
2021-05-27 15:49     ` Morten Brørup
2021-05-27 16:25       ` Bruce Richardson
2021-05-27 17:09         ` Manish Sharma
2021-05-27 17:22           ` Bruce Richardson
2021-05-27 18:15             ` Morten Brørup
2021-06-22 21:55               ` Morten Brørup

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