RE: [PATCH 3/3] net/mlx5: support enhanced multi-packet write on Windows

[Pier Damouny <pdamouny@nvidia.com>]

> Subject: [PATCH 3/3] net/mlx5: support enhanced multi-packet write on
> Windows
> 
> Add support for enhanced multi-packet write on Windows.
> 
> Enhanced multi-packet write allows the Tx burst function to pack up multiple
> packets in a single descriptor session to save PCI bandwidth and improve
> performance.
> 
> The feature can be controlled by the txq_mpw_en PMD argument:
> 
> txq_mpw_en=1 - PMD will first attempt to use "enhanced multi packet
> write"
> if the feature is not supported by the HW the legacy "multi packet write"
> will be used.
> if both are unsupported the multi packet write feature is disabled.
> 
> txq_mpw_en=0 - multi packet write is disabled.
> 
> txq_mpw_en unset(default) - enhanced multi packet write will be activated
> if supported.
> if unsupported the multi packet write feature is disabled.
> 
> Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
> ---
>  doc/guides/rel_notes/release_23_07.rst | 33 ++++-----------------------------
>  drivers/common/mlx5/mlx5_devx_cmds.c   |  6 ++++++
>  drivers/common/mlx5/mlx5_devx_cmds.h   |  2 ++
>  drivers/net/mlx5/windows/mlx5_os.c     |  8 +++++++-
>  4 files changed, 19 insertions(+), 30 deletions(-)
> 
> diff --git a/doc/guides/rel_notes/release_23_07.rst
> b/doc/guides/rel_notes/release_23_07.rst
> index a9b1293689..d74551414d 100644
> --- a/doc/guides/rel_notes/release_23_07.rst
> +++ b/doc/guides/rel_notes/release_23_07.rst
> @@ -24,36 +24,11 @@ DPDK Release 23.07
>  New Features
>  ------------
> 
> -.. This section should contain new features added in this release.
> -   Sample format:
> +* **Updated NVIDIA mlx5 driver.**
> 
> -   * **Add a title in the past tense with a full stop.**
> -
> -     Add a short 1-2 sentence description in the past tense.
> -     The description should be enough to allow someone scanning
> -     the release notes to understand the new feature.
> -
> -     If the feature adds a lot of sub-features you can use a bullet list
> -     like this:
> -
> -     * Added feature foo to do something.
> -     * Enhanced feature bar to do something else.
> -
> -     Refer to the previous release notes for examples.
> -
> -     Suggested order in release notes items:
> -     * Core libs (EAL, mempool, ring, mbuf, buses)
> -     * Device abstraction libs and PMDs (ordered alphabetically by vendor
> name)
> -       - ethdev (lib, PMDs)
> -       - cryptodev (lib, PMDs)
> -       - eventdev (lib, PMDs)
> -       - etc
> -     * Other libs
> -     * Apps, Examples, Tools (if significant)
> -
> -     This section is a comment. Do not overwrite or remove it.
> -     Also, make sure to start the actual text at the margin.
> -     =======================================================
> +  * Added support for multi-packet RQ on Windows.
> +  * Added support for CQE compression on Windows.
> +  * Added support for enhanced multi-packet write on Windows.
> 
> 
>  Removed Items
> diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c
> b/drivers/common/mlx5/mlx5_devx_cmds.c
> index a31e4995f5..b2abc742cf 100644
> --- a/drivers/common/mlx5/mlx5_devx_cmds.c
> +++ b/drivers/common/mlx5/mlx5_devx_cmds.c
> @@ -1298,6 +1298,12 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
>  	attr->rss_ind_tbl_cap = MLX5_GET
> 
> 	(per_protocol_networking_offload_caps,
>  					 hcattr, rss_ind_tbl_cap);
> +	attr->multi_pkt_send_wqe = MLX5_GET
> +
> 	(per_protocol_networking_offload_caps,
> +					 hcattr, multi_pkt_send_wqe);
> +	attr->enhanced_multi_pkt_send_wqe = MLX5_GET
> +
> 	(per_protocol_networking_offload_caps,
> +					 hcattr,
> enhanced_multi_pkt_send_wqe);
>  	/* Query HCA attribute for ROCE. */
>  	if (attr->roce) {
>  		hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, diff --git
> a/drivers/common/mlx5/mlx5_devx_cmds.h
> b/drivers/common/mlx5/mlx5_devx_cmds.h
> index edcd867c4e..c8427d2dbb 100644
> --- a/drivers/common/mlx5/mlx5_devx_cmds.h
> +++ b/drivers/common/mlx5/mlx5_devx_cmds.h
> @@ -285,6 +285,8 @@ struct mlx5_hca_attr {
>  	uint32_t striding_rq:1;
>  	uint32_t ext_stride_num_range:1;
>  	uint32_t cqe_compression_128:1;
> +	uint32_t multi_pkt_send_wqe:1;
> +	uint32_t enhanced_multi_pkt_send_wqe:1;
>  	uint32_t set_reg_c:8;
>  	uint32_t nic_flow_table:1;
>  	uint32_t modify_outer_ip_ecn:1;
> diff --git a/drivers/net/mlx5/windows/mlx5_os.c
> b/drivers/net/mlx5/windows/mlx5_os.c
> index 6527269663..b731bdff06 100644
> --- a/drivers/net/mlx5/windows/mlx5_os.c
> +++ b/drivers/net/mlx5/windows/mlx5_os.c
> @@ -173,7 +173,6 @@ mlx5_os_capabilities_prepare(struct
> mlx5_dev_ctx_shared *sh)
>  	sh->dev_cap.max_qp = 1 << hca_attr->log_max_qp;
>  	sh->dev_cap.max_qp_wr = 1 << hca_attr->log_max_qp_sz;
>  	sh->dev_cap.dv_flow_en = 1;
> -	sh->dev_cap.mps = MLX5_MPW_DISABLED;
>  	DRV_LOG(DEBUG, "MPW isn't supported.");
>  	DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is no
> supported.");
>  	sh->dev_cap.hw_csum = hca_attr->csum_cap; @@ -224,6 +223,13
> @@ mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh)
>  		DRV_LOG(DEBUG, "Maximum Rx indirection table size is %u",
>  			sh->dev_cap.ind_table_max_size);
>  	}
> +	if (hca_attr->enhanced_multi_pkt_send_wqe)
> +		sh->dev_cap.mps = MLX5_MPW_ENHANCED;
> +	else if (hca_attr->multi_pkt_send_wqe &&
> +		 sh->dev_cap.mps != MLX5_ARG_UNSET)
> +		sh->dev_cap.mps = MLX5_MPW;
> +	else
> +		sh->dev_cap.mps = MLX5_MPW_DISABLED;
>  	sh->dev_cap.swp =
> mlx5_get_supported_sw_parsing_offloads(hca_attr);
>  	sh->dev_cap.tunnel_en =
> mlx5_get_supported_tunneling_offloads(hca_attr);
>  	if (sh->dev_cap.tunnel_en) {
> --
> 2.16.1.windows.4

Tested-by: Pier Damouny  <pdamouny@nvidia.com>