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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CH3PR11MB8362.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 628cf905-e196-4e39-ac17-08dbafa4a246 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Sep 2023 13:16:23.4558 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: JBqnApJdoO3uUyjdUdd9J/iecIatX7IEmUTAK8oBmnkDRQiFAsy8wuXkoQ9+WCeRxRyis5rLGc8GlEVBsPiyEw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR11MB7659 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: David Marchand > Sent: Monday, August 21, 2023 7:36 PM > To: dev@dpdk.org > Cc: thomas@monjalon.net; ferruh.yigit@amd.com; Xia, Chenbo > ; nipun.gupta@amd.com; Richardson, Bruce > ; Julien Aube ; Gaetan > Rivet > Subject: [PATCH v2 09/15] pci: define some PM constants >=20 > Define some PCI Power Management constants and use them in existing > drivers. >=20 > Signed-off-by: David Marchand > Acked-by: Bruce Richardson > --- > drivers/net/bnx2x/bnx2x.c | 17 +++++++++-------- > drivers/net/bnx2x/bnx2x.h | 5 ----- > lib/pci/rte_pci.h | 6 ++++++ > 3 files changed, 15 insertions(+), 13 deletions(-) >=20 > diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c > index e3f14400cc..faf061beba 100644 > --- a/drivers/net/bnx2x/bnx2x.c > +++ b/drivers/net/bnx2x/bnx2x.c > @@ -5843,17 +5843,17 @@ static int bnx2x_set_power_state(struct > bnx2x_softc *sc, uint8_t state) > return 0; > } >=20 > - pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), > &pmcsr, > + pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + RTE_PCI_PM_CTRL), &pmcsr, > 2); >=20 > switch (state) { > case PCI_PM_D0: > pci_write_word(sc, > (sc->devinfo.pcie_pm_cap_reg + > - PCIR_POWER_STATUS), > - ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME)); > + RTE_PCI_PM_CTRL), > + ((pmcsr & ~RTE_PCI_PM_CTRL_STATE_MASK) | > RTE_PCI_PM_CTRL_PME_STATUS)); >=20 > - if (pmcsr & PCIM_PSTAT_DMASK) { > + if (pmcsr & RTE_PCI_PM_CTRL_STATE_MASK) { > /* delay required during transition out of D3hot */ > DELAY(20000); > } > @@ -5866,16 +5866,17 @@ static int bnx2x_set_power_state(struct > bnx2x_softc *sc, uint8_t state) > return 0; > } >=20 > - pmcsr &=3D ~PCIM_PSTAT_DMASK; > - pmcsr |=3D PCIM_PSTAT_D3; > + pmcsr &=3D ~RTE_PCI_PM_CTRL_STATE_MASK; > + /* D3 power state */ > + pmcsr |=3D 0x3; >=20 > if (sc->wol) { > - pmcsr |=3D PCIM_PSTAT_PMEENABLE; > + pmcsr |=3D RTE_PCI_PM_CTRL_PME_ENABLE; > } >=20 > pci_write_long(sc, > (sc->devinfo.pcie_pm_cap_reg + > - PCIR_POWER_STATUS), pmcsr); > + RTE_PCI_PM_CTRL), pmcsr); >=20 > /* > * No more memory access after this point until device is > brought back > diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h > index 60af75d336..1efa166316 100644 > --- a/drivers/net/bnx2x/bnx2x.h > +++ b/drivers/net/bnx2x/bnx2x.h > @@ -41,11 +41,6 @@ > #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL > #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD > #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ > -#define PCIR_POWER_STATUS PCI_PM_CTRL > -#define PCIM_PSTAT_DMASK PCI_PM_CTRL_STATE_MASK > -#define PCIM_PSTAT_PME PCI_PM_CTRL_PME_STATUS > -#define PCIM_PSTAT_D3 0x3 > -#define PCIM_PSTAT_PMEENABLE PCI_PM_CTRL_PME_ENABLE > #else > #include > #endif > diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h > index 62bf87aa10..542d142dfb 100644 > --- a/lib/pci/rte_pci.h > +++ b/lib/pci/rte_pci.h > @@ -57,6 +57,12 @@ extern "C" { > #define RTE_PCI_CAP_ID_MSIX 0x11 /* MSI-X */ > #define RTE_PCI_CAP_SIZEOF 4 >=20 > +/* Power Management Registers (RTE_PCI_CAP_ID_PM) */ > +#define RTE_PCI_PM_CTRL 4 /* PM control and status > register */ > +#define RTE_PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 > to D3) */ > +#define RTE_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ > +#define RTE_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ > + > /* MSI-X registers (RTE_PCI_CAP_ID_MSIX) */ > #define RTE_PCI_MSIX_FLAGS 2 /* Message Control */ > #define RTE_PCI_MSIX_FLAGS_QSIZE 0x07ff /* Table size */ > -- > 2.41.0 Reviewed-by: Chenbo Xia =20