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From: Maayan Kashani <mkashani@nvidia.com>
To: Maayan Kashani <mkashani@nvidia.com>, "dev@dpdk.org" <dev@dpdk.org>
Cc: Raslan Darawsheh <rasland@nvidia.com>,
	Dariusz Sosnowski <dsosnowski@nvidia.com>,
	Slava Ovsiienko <viacheslavo@nvidia.com>,
	Bing Zhao <bingz@nvidia.com>, Ori Kam <orika@nvidia.com>,
	Suanming Mou <suanmingm@nvidia.com>,
	Matan Azrad <matan@nvidia.com>
Subject: RE: [PATCH 2/2] net/mlx5: update flow devarg handling for future HW
Date: Mon, 24 Nov 2025 09:01:32 +0000	[thread overview]
Message-ID: <CH3PR12MB8074386185825633E3F6EBEBB2D0A@CH3PR12MB8074.namprd12.prod.outlook.com> (raw)
In-Reply-To: <IA1PR12MB807706F52B5D84500C3F78C7B2D0A@IA1PR12MB8077.namprd12.prod.outlook.com>

The series should be reverted,
the series is handling untrusted VF's/SF's same as CX9,
Using HWS engine and causing a degradation
(failed to probe 1K SF's cause memzone segments exceeds maximum 2560).

Regards,
Maayan Kashani

> -----Original Message-----
> From: Maayan Kashani <mkashani@nvidia.com>
> Sent: Monday, 24 November 2025 10:30
> To: dev@dpdk.org
> Cc: Raslan Darawsheh <rasland@nvidia.com>; Dariusz Sosnowski
> <dsosnowski@nvidia.com>; Slava Ovsiienko <viacheslavo@nvidia.com>; Bing
> Zhao <bingz@nvidia.com>; Ori Kam <orika@nvidia.com>; Suanming Mou
> <suanmingm@nvidia.com>; Matan Azrad <matan@nvidia.com>
> Subject: RE: [PATCH 2/2] net/mlx5: update flow devarg handling for future
> HW
> 
> External email: Use caution opening links or attachments
> 
> 
> Hi,
> Please revert this series.
> 
> Regards,
> Maayan Kashani
> 
> > -----Original Message-----
> > From: Maayan Kashani <mkashani@nvidia.com>
> > Sent: Thursday, 6 November 2025 10:38
> > To: dev@dpdk.org
> > Cc: Maayan Kashani <mkashani@nvidia.com>; Raslan Darawsheh
> > <rasland@nvidia.com>; Dariusz Sosnowski <dsosnowski@nvidia.com>;
> Slava
> > Ovsiienko <viacheslavo@nvidia.com>; Bing Zhao <bingz@nvidia.com>; Ori
> > Kam <orika@nvidia.com>; Suanming Mou <suanmingm@nvidia.com>;
> Matan
> > Azrad <matan@nvidia.com>
> > Subject: [PATCH 2/2] net/mlx5: update flow devarg handling for future
> > HW
> >
> > SWS (software steering) will be disabled on future hardware generations.
> > Update the defaults for the dv_flow_en and allow_duplicate_pattern
> > devargs accordingly.
> >
> > - Default dv_flow_en devarg value will be chosen based on whether
> >   NIC supports SW steering and/or HW steering.
> > - If DV flow is not supported and allow_duplicate_pattern is
> >   set by the user, forcibly disable it and emit a clear log message.
> >
> > This change improves reliability by ensuring only valid configurations
> > are applied, and provides clear feedback to the user when fallbacks
> > are triggered.
> >
> > Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
> > Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
> > ---
> >  doc/guides/nics/mlx5.rst | 11 +++++--  drivers/net/mlx5/mlx5.c  | 71
> > ++++++++++++++++++++++++++++++++++++++-
> > -
> >  2 files changed, 77 insertions(+), 5 deletions(-)
> >
> > diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index
> > 37495359d4f..91983089702 100644
> > --- a/doc/guides/nics/mlx5.rst
> > +++ b/doc/guides/nics/mlx5.rst
> > @@ -694,8 +694,11 @@ for an additional list of options shared with
> > other
> > mlx5 drivers.
> >    Value 2 enables the WQE based hardware steering.
> >    In this mode, only queue-based flow management is supported.
> >
> > -  It is configured by default to 1 (DV flow steering) if supported.
> > -  Otherwise, the value is 0 which indicates legacy Verbs flow offloading.
> > +  By default, the PMD will set this value according to capability.
> > +  If DV flow steering is supported, it will be set to 1.
> > +  If DV flow steering is not supported and HW steering is supported,
> > + then it will be set to 2.
> > +  Otherwise, it will be set to 0.
> >
> >  - ``dv_esw_en`` parameter [int]
> >
> > @@ -838,8 +841,10 @@ for an additional list of options shared with
> > other
> > mlx5 drivers.
> >    - 1. Allow insertion of rules with the same pattern items.
> >      In this case, all rules are inserted but only the first rule takes effect,
> >      the next rule takes effect only if the previous rules are deleted.
> > +    This option is not supported in :ref:`HWS mode <mlx5_hws>`.
> > +    If this option is set to 1 in HWS mode, it will be set to 0.
> >
> > -  By default, the PMD will set this value to 1.
> > +  By default, the PMD will set this value according to capability.
> >
> >
> >  .. _mlx5_net_stats:
> > diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index
> > ea235cf36be..dd3460f8d4b 100644
> > --- a/drivers/net/mlx5/mlx5.c
> > +++ b/drivers/net/mlx5/mlx5.c
> > @@ -1443,6 +1443,45 @@ mlx5_dev_args_check_handler(const char *key,
> > const char *val, void *opaque)
> >       return 0;
> >  }
> >
> > +static bool
> > +mlx5_hws_is_supported(struct mlx5_dev_ctx_shared *sh) {
> > +     return (sh->cdev->config.devx &&
> > +            sh->cdev->config.hca_attr.wqe_based_flow_table_sup);
> > +}
> > +
> > +static bool
> > +mlx5_sws_is_any_supported(struct mlx5_dev_ctx_shared *sh) {
> > +     struct mlx5_common_device *cdev = sh->cdev;
> > +     struct mlx5_hca_attr *hca_attr = &cdev->config.hca_attr;
> > +
> > +     if (hca_attr->rx_sw_owner_v2 || hca_attr->rx_sw_owner)
> > +             return true;
> > +
> > +     if (hca_attr->tx_sw_owner_v2 || hca_attr->tx_sw_owner)
> > +             return true;
> > +
> > +     if (hca_attr->eswitch_manager && (hca_attr->esw_sw_owner_v2 ||
> > hca_attr->esw_sw_owner))
> > +             return true;
> > +
> > +     return false;
> > +}
> > +
> > +static bool
> > +mlx5_kvargs_is_used(struct mlx5_kvargs_ctrl *mkvlist, const char
> > +*key) {
> > +     const struct rte_kvargs_pair *pair;
> > +     uint32_t i;
> > +
> > +     for (i = 0; i < mkvlist->kvlist->count; ++i) {
> > +             pair = &mkvlist->kvlist->pairs[i];
> > +             if (strcmp(pair->key, key) == 0 && mkvlist->is_used[i])
> > +                     return true;
> > +     }
> > +     return false;
> > +}
> > +
> >  /**
> >   * Parse user device parameters and adjust them according to device
> >   * capabilities.
> > @@ -1484,6 +1523,8 @@ mlx5_shared_dev_ctx_args_config(struct
> > mlx5_dev_ctx_shared *sh,
> >       int ret = 0;
> >       size_t alignment = rte_mem_page_size();
> >       uint32_t max_queue_umem_size = MLX5_WQE_SIZE *
> > mlx5_dev_get_max_wq_size(sh);
> > +     bool hws_is_supported = mlx5_hws_is_supported(sh);
> > +     bool sws_is_supported = mlx5_sws_is_any_supported(sh);
> >
> >       if (alignment == (size_t)-1) {
> >               alignment = (1 << MLX5_LOG_PAGE_SIZE); @@ -1494,9
> > +1535,15 @@ mlx5_shared_dev_ctx_args_config(struct
> > mlx5_dev_ctx_shared *sh,
> >       memset(config, 0, sizeof(*config));
> >       config->vf_nl_en = 1;
> >       config->dv_esw_en = 1;
> > -     config->dv_flow_en = 1;
> > +     if (!sws_is_supported && hws_is_supported)
> > +             config->dv_flow_en = 2;
> > +     else
> > +             config->dv_flow_en = 1;
> >       config->decap_en = 1;
> > -     config->allow_duplicate_pattern = 1;
> > +     if (config->dv_flow_en == 2)
> > +             config->allow_duplicate_pattern = 0;
> > +     else
> > +             config->allow_duplicate_pattern = 1;
> >       config->fdb_def_rule = 1;
> >       config->cnt_svc.cycle_time = MLX5_CNT_SVC_CYCLE_TIME_DEFAULT;
> >       config->cnt_svc.service_core = rte_get_main_lcore(); @@ -1517,6
> > +1564,26 @@ mlx5_shared_dev_ctx_args_config(struct
> > mlx5_dev_ctx_shared *sh,
> >               DRV_LOG(WARNING, "DV flow is not supported.");
> >               config->dv_flow_en = 0;
> >       }
> > +     /* Inform user if DV flow is not supported. */
> > +     if (config->dv_flow_en == 1 && !sws_is_supported &&
> > hws_is_supported) {
> > +             DRV_LOG(WARNING, "DV flow is not supported. Changing to
> > HWS mode.");
> > +             config->dv_flow_en = 2;
> > +     }
> > +     /* Handle allow_duplicate_pattern based on final dv_flow_en mode.
> > +      * HWS mode (dv_flow_en=2) doesn't support duplicate patterns.
> > +      * Warn only if user explicitly requested an incompatible setting.
> > +      */
> > +     bool allow_dup_pattern_set = mkvlist != NULL &&
> > +             mlx5_kvargs_is_used(mkvlist,
> > MLX5_ALLOW_DUPLICATE_PATTERN);
> > +     if (config->dv_flow_en == 2) {
> > +             if (config->allow_duplicate_pattern == 1 &&
> > allow_dup_pattern_set)
> > +                     DRV_LOG(WARNING, "Duplicate pattern is not
> > supported with HWS. Disabling it.");
> > +             config->allow_duplicate_pattern = 0;
> > +     } else if (!allow_dup_pattern_set) {
> > +             /* Non-HWS mode: set default to 1 only if not explicitly
> > + set by
> > user */
> > +             config->allow_duplicate_pattern = 1;
> > +     }
> > +
> >       if (config->dv_esw_en && !sh->dev_cap.dv_esw_en) {
> >               DRV_LOG(DEBUG, "E-Switch DV flow is not supported.");
> >               config->dv_esw_en = 0;
> > --
> > 2.21.0


  reply	other threads:[~2025-11-24  9:01 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-06  8:38 [PATCH 1/2] common/mlx5: read SWS capability bits Maayan Kashani
2025-11-06  8:38 ` [PATCH 2/2] net/mlx5: update flow devarg handling for future HW Maayan Kashani
2025-11-24  8:29   ` Maayan Kashani
2025-11-24  9:01     ` Maayan Kashani [this message]
2025-11-16 15:27 ` [PATCH 1/2] common/mlx5: read SWS capability bits Raslan Darawsheh

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