[PATCH] net/mlx5: fix GTP flags matching

[PATCH] net/mlx5: fix GTP flags matching

[Maayan Kashani]

Support gtp flags in non template on top of HWS.
Currently, only extension flag was supported,
Added support to all bits under v_pt_rsv_flags.

Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer")
Cc: stable@dpdk.org

Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c | 12 ++++++------
 drivers/net/mlx5/hws/mlx5dr_definer.h | 18 ++++++++++++------
 2 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 98d670fc1ce..d7799888b1f 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -199,7 +199,7 @@ struct mlx5dr_definer_conv_data {
 	X(SET,		gtp_udp_port,		UDP_GTPU_PORT,		rte_flow_item_gtp) \
 	X(SET_BE32,	gtp_teid,		v->hdr.teid,		rte_flow_item_gtp) \
 	X(SET,		gtp_msg_type,		v->hdr.msg_type,	rte_flow_item_gtp) \
-	X(SET,		gtp_ext_flag,		!!v->hdr.gtp_hdr_info,	rte_flow_item_gtp) \
+	X(SET,		gtp_flags,		v->hdr.gtp_hdr_info,	rte_flow_item_gtp) \
 	X(SET,		gtp_next_ext_hdr,	GTP_PDU_SC,		rte_flow_item_gtp_psc) \
 	X(SET,		gtp_ext_hdr_pdu,	v->hdr.type,		rte_flow_item_gtp_psc) \
 	X(SET,		gtp_ext_hdr_qfi,	v->hdr.qfi,		rte_flow_item_gtp_psc) \
@@ -1462,7 +1462,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd,
 	if (!m)
 		return 0;
 
-	if (m->hdr.plen || m->hdr.gtp_hdr_info & ~MLX5DR_DEFINER_GTP_EXT_HDR_BIT) {
+	if (m->msg_len) {
 		rte_errno = ENOTSUP;
 		return rte_errno;
 	}
@@ -1484,11 +1484,11 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd,
 			rte_errno = ENOTSUP;
 			return rte_errno;
 		}
-		fc = &cd->fc[MLX5DR_DEFINER_FNAME_GTP_EXT_FLAG];
+		fc = &cd->fc[MLX5DR_DEFINER_FNAME_GTP_FLAGS];
 		fc->item_idx = item_idx;
-		fc->tag_set = &mlx5dr_definer_gtp_ext_flag_set;
-		fc->bit_mask = __mlx5_mask(header_gtp, ext_hdr_flag);
-		fc->bit_off = __mlx5_dw_bit_off(header_gtp, ext_hdr_flag);
+		fc->tag_set = &mlx5dr_definer_gtp_flags_set;
+		fc->bit_mask = __mlx5_mask(header_gtp, v_pt_rsv_flags);
+		fc->bit_off = __mlx5_dw_bit_off(header_gtp, v_pt_rsv_flags);
 		fc->byte_off = caps->format_select_gtpu_dw_0 * DW_SIZE;
 	}
 
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index 092b1b3b10e..d0c99399ae5 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -110,6 +110,7 @@ enum mlx5dr_definer_fname {
 	MLX5DR_DEFINER_FNAME_GTP_TEID,
 	MLX5DR_DEFINER_FNAME_GTP_MSG_TYPE,
 	MLX5DR_DEFINER_FNAME_GTP_EXT_FLAG,
+	MLX5DR_DEFINER_FNAME_GTP_FLAGS,
 	MLX5DR_DEFINER_FNAME_GTP_NEXT_EXT_HDR,
 	MLX5DR_DEFINER_FNAME_GTP_EXT_HDR_PDU,
 	MLX5DR_DEFINER_FNAME_GTP_EXT_HDR_QFI,
@@ -606,12 +607,17 @@ enum mlx5dr_definer_gtp {
 };
 
 struct mlx5_ifc_header_gtp_bits {
-	u8 version[0x3];
-	u8 proto_type[0x1];
-	u8 reserved1[0x1];
-	u8 ext_hdr_flag[0x1];
-	u8 seq_num_flag[0x1];
-	u8 pdu_flag[0x1];
+	union {
+		 u8 v_pt_rsv_flags[0x8];
+		struct {
+			u8 version[0x3];
+			u8 proto_type[0x1];
+			u8 reserved1[0x1];
+			u8 ext_hdr_flag[0x1];
+			u8 seq_num_flag[0x1];
+			u8 pdu_flag[0x1];
+		};
+	};
 	u8 msg_type[0x8];
 	u8 msg_len[0x8];
 	u8 teid[0x20];
-- 
2.21.0

Re: [PATCH] net/mlx5: fix GTP flags matching

[Raslan Darawsheh]

Hi,

From: Maayan Kashani <mkashani@nvidia.com>
Sent: Thursday, February 27, 2025 12:49 PM
To: dev@dpdk.org
Cc: Maayan Kashani; Dariusz Sosnowski; Raslan Darawsheh; stable@dpdk.org; Slava Ovsiienko; Bing Zhao; Ori Kam; Suanming Mou; Matan Azrad; Alex Vesker; Mark Bloch
Subject: [PATCH] net/mlx5: fix GTP flags matching

Support gtp flags in non template on top of HWS.
Currently, only extension flag was supported,
Added support to all bits under v_pt_rsv_flags.

Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer")
Cc: stable@dpdk.org

Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh