From: Raslan Darawsheh <rasland@nvidia.com>
To: Gregory Etelson <getelson@nvidia.com>, "dev@dpdk.org" <dev@dpdk.org>
Cc: Maayan Kashani <mkashani@nvidia.com>,
Bing Zhao <bingz@nvidia.com>, "stable@dpdk.org" <stable@dpdk.org>
Subject: Re: [PATCH] net/mlx5: fix the GRE mask set on root table
Date: Mon, 10 Feb 2025 10:33:10 +0000 [thread overview]
Message-ID: <CH3PR12MB84603C0D9C4F47DAC57E33A0CFF22@CH3PR12MB8460.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20250210101457.306368-1-getelson@nvidia.com>
Hi,
From: Gregory Etelson <getelson@nvidia.com>
Sent: Monday, February 10, 2025 12:14 PM
To: dev@dpdk.org
Cc: Gregory Etelson; Maayan Kashani; Raslan Darawsheh; Bing Zhao; stable@dpdk.org
Subject: [PATCH] net/mlx5: fix the GRE mask set on root table
From: Bing Zhao <bingz@nvidia.com>
When setting the value, the GRE mask cannot reuse the one from the
value, or else the value cannot be really ANDed with the proper input
mask from the user. If the value contains more valid bits than the
mask, the rule insertion on the root table will get a failure due to
the extra bits in the value field.
Using the input mask or the default mask will help to clear the extra
bits and solve the issue.
Fixes: 25ab2cbba31d ("net/mlx5: fix GRE item translation for root table")
cc: stable@dpdk.org
Signed-off-by: Bing Zhao <bingz@nvidia.com>
dropping this patch as it's a duplicate of this:
https://patches.dpdk.org/project/dpdk/patch/20250128075930.175636-1-mkashani@nvidia.com/
Kindest regards
Raslan Darawsheh
prev parent reply other threads:[~2025-02-10 10:33 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-10 10:14 Gregory Etelson
2025-02-10 10:33 ` Raslan Darawsheh [this message]
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