From: Raslan Darawsheh <rasland@nvidia.com>
To: Dariusz Sosnowski <dsosnowski@nvidia.com>,
Slava Ovsiienko <viacheslavo@nvidia.com>,
Bing Zhao <bingz@nvidia.com>, Ori Kam <orika@nvidia.com>,
Suanming Mou <suanmingm@nvidia.com>,
Matan Azrad <matan@nvidia.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>, "stable@dpdk.org" <stable@dpdk.org>
Subject: Re: [PATCH] net/mlx5: fix NAT64 register selection
Date: Thu, 13 Mar 2025 13:07:56 +0000 [thread overview]
Message-ID: <CH3PR12MB8460CB6585782E5E6F4F8B4BCFD32@CH3PR12MB8460.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20250312095108.105978-1-dsosnowski@nvidia.com>
Hi
From: Dariusz Sosnowski <dsosnowski@nvidia.com>
Sent: Wednesday, March 12, 2025 11:51 AM
To: Slava Ovsiienko; Bing Zhao; Ori Kam; Suanming Mou; Matan Azrad
Cc: dev@dpdk.org; Raslan Darawsheh; stable@dpdk.org
Subject: [PATCH] net/mlx5: fix NAT64 register selection
PMD statically assumed that REG_C_6 is always available for use
with NAT64 HW flow action.
This led to PMD configuration errors on FW versions which do not expose
that specific register.
This patch fixes that by adding a check for REG_C_6 against FW
capabilities, when registers for NAT64 are selected.
Also, if not enough registers are available, PMD will not attempt to
create NAT64 actions.
Fixes: 7a26bfec06a4 ("net/mlx5: fetch available registers for NAT64")
Cc: stable@dpdk.org
Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
prev parent reply other threads:[~2025-03-13 13:08 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-12 9:51 Dariusz Sosnowski
2025-03-13 13:07 ` Raslan Darawsheh [this message]
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