From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 909C3A034C; Thu, 1 Sep 2022 21:08:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2CC7440693; Thu, 1 Sep 2022 21:08:20 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 9577E40684 for ; Thu, 1 Sep 2022 21:08:18 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 281DsBZa016118; Thu, 1 Sep 2022 12:08:17 -0700 Received: from nam10-dm6-obe.outbound.protection.outlook.com (mail-dm6nam10lp2100.outbound.protection.outlook.com [104.47.58.100]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3jax17sbea-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 01 Sep 2022 12:08:17 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jYp5miS1SMK+X9BnyAtnDBQd8/AVIwYki6OLp9NYhBMluEsI7G8U6cOR0qPyYNjrEeMsecNJtqoWgHM4RbHMdGnE4nmiDV/E3alYnzzCR01o9YvZve5VuANuMBM0LUqZLilGzSE4bPBGzg7GiCvL4U2v3AZHn7kQemdVktCgMzXysKRu8JDHrOrHngdKk95/A13FRdWkkyLlmzYyPq6vmbXVooTyLPxs+cKTzmlSsSzsTmK40Kx1K8MGD6FSVQ7uWYPMswksWw0Ur7hDpxwY3SaqXbYLIrUAZCjjwL8DAUE0Q5ZUeN2rYbUMVPNzt//6xQ+LnEQjUJgSffLBnp9upA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VSfcpkT1Q3npVQrM8kC13dSzEQ4fnh8WrNnjo8vGzuA=; b=Z409382veK638+wQXekvf3dBHmfTKMEw4vsqJGcu0+f4ElCoU5QkhkHrVtabsW+saLz+LLoo57nr9xbDOYudrdi9aXI73RNKnkkVLNoGZFPgJHSvaT+h7paboHUdbOy7FUXZyQww3AFjKHdoVRXg3EyHoSSRHav7+89OXhaf2UPctXJ22ltbOjERY7SvdgYgLgKTNZYdqONUzBDqEsKQ7RXnXTekvmwdmrt36gTr8ensc8gQEwxvLa134pYTB2QaqRmYjw/UHCa/CKkRGV8PviQBSb0rKcFYXo4yHwP5bkIg2CY89kMgt7rFvA68PcR7KV70kwiuddQBzkckd5Qsog== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=marvell.com; dmarc=pass action=none header.from=marvell.com; dkim=pass header.d=marvell.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.onmicrosoft.com; s=selector1-marvell-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VSfcpkT1Q3npVQrM8kC13dSzEQ4fnh8WrNnjo8vGzuA=; b=tx4IKYZyqXlX8ehrUe0DeZEvlXkTcAjRe1B1bCMaed4rqENs7PldM8LV8hWloTi41UWflha8VkiUultH1KJNgyxMaCOYZE6Beh5OJU5aVJ9psLENCZSmnfEt81vBieR5nQbY9REEb7rKUyTnofDBWK4LzyTOFfvFlDjb7rTHnD0= Received: from CO1PR18MB4732.namprd18.prod.outlook.com (2603:10b6:303:eb::13) by SJ0PR18MB4997.namprd18.prod.outlook.com (2603:10b6:a03:3e8::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5588.10; Thu, 1 Sep 2022 19:08:15 +0000 Received: from CO1PR18MB4732.namprd18.prod.outlook.com ([fe80::f0cf:3806:623f:9be5]) by CO1PR18MB4732.namprd18.prod.outlook.com ([fe80::f0cf:3806:623f:9be5%5]) with mapi id 15.20.5588.012; Thu, 1 Sep 2022 19:08:15 +0000 From: Radha Chintakuntla To: Radha Chintakuntla , "dev@dpdk.org" CC: "thomas@monjalon.net" , Nithin Kumar Dabilpuram , Kiran Kumar Kokkilagadda , Sunil Kumar Kori , Satha Koteswara Rao Kottidi , Veerasenareddy Burru Subject: RE: [PATCH v3] dma/cnxk: add support for CN10K DMA engine Thread-Topic: [PATCH v3] dma/cnxk: add support for CN10K DMA engine Thread-Index: AQHYqQHOauulzWC48ke1yW2G/UzpA63LGhbA Date: Thu, 1 Sep 2022 19:08:14 +0000 Message-ID: References: <20220805185715.22862-1-radhac@marvell.com> <20220805193007.26020-1-radhac@marvell.com> In-Reply-To: <20220805193007.26020-1-radhac@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-dg-ref: =?us-ascii?Q?PG1ldGE+PGF0IG5tPSJib2R5LnR4dCIgcD0iYzpcdXNlcnNccmFkaGFjXGFw?= =?us-ascii?Q?cGRhdGFccm9hbWluZ1wwOWQ4NDliNi0zMmQzLTRhNDAtODVlZS02Yjg0YmEy?= =?us-ascii?Q?OWUzNWJcbXNnc1xtc2ctNmI1NDA5ZGItMmEyOS0xMWVkLTljM2ItOGMxZDk2?= =?us-ascii?Q?ZjRjN2ExXGFtZS10ZXN0XDZiNTQwOWRjLTJhMjktMTFlZC05YzNiLThjMWQ5?= =?us-ascii?Q?NmY0YzdhMWJvZHkudHh0IiBzej0iMTUzNzkiIHQ9IjEzMzA2NTMyODkzMDU4?= =?us-ascii?Q?MzIwMSIgaD0iUGx4SUF5VGNFL2U2VFFVWk85VzFtY0I0K1VNPSIgaWQ9IiIg?= =?us-ascii?Q?Ymw9IjAiIGJvPSIxIiBjaT0iY0FBQUFFUkhVMVJTUlVGTkNnVUFBUDRGQUFD?= =?us-ascii?Q?aDh0TXVOcjdZQVNJVFhhc1FCeTVxSWhOZHF4QUhMbW9KQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUhBQUFBQ09CUUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUVBQVFBQkFBQUFFQ0Y3WEFBQUFBQUFBQUFBQUFBQUFKNEFBQUJoQUdRQVpB?= =?us-ascii?Q?QnlBR1VBY3dCekFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFFQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?RUFBQUFBQUFBQUFnQUFBQUFBbmdBQUFHTUFkUUJ6QUhRQWJ3QnRBRjhBY0FC?= =?us-ascii?Q?bEFISUFjd0J2QUc0QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQVFBQUFBQUFBQUFDQUFB?= =?us-ascii?Q?QUFBQ2VBQUFBWXdCMUFITUFkQUJ2QUcwQVh3QndBR2dBYndCdUFHVUFiZ0Ix?= =?us-ascii?Q?QUcwQVlnQmxBSElBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUJBQUFBQUFBQUFBSUFBQUFBQUo0QUFBQmpBSFVB?= =?us-ascii?Q?Y3dCMEFHOEFiUUJmQUhNQWN3QnVBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= x-dg-refone: =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFFQUFBQUFBQUFBQWdBQUFBQUFuZ0FBQUdR?= =?us-ascii?Q?QWJBQndBRjhBY3dCckFIa0FjQUJsQUY4QVl3Qm9BR0VBZEFCZkFHMEFaUUJ6?= =?us-ascii?Q?QUhNQVlRQm5BR1VBWHdCMkFEQUFNZ0FBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBUUFBQUFBQUFBQUNBQUFBQUFDZUFBQUFaQUJzQUhBQVh3QnpBR3dB?= =?us-ascii?Q?WVFCakFHc0FYd0JqQUdnQVlRQjBBRjhBYlFCbEFITUFjd0JoQUdjQVpRQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQkFBQUFBQUFB?= =?us-ascii?Q?QUFJQUFBQUFBSjRBQUFCa0FHd0FjQUJmQUhRQVpRQmhBRzBBY3dCZkFHOEFi?= =?us-ascii?Q?Z0JsQUdRQWNnQnBBSFlBWlFCZkFHWUFhUUJzQUdVQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUVBQUFBQUFBQUFBZ0FBQUFBQW5nQUFB?= =?us-ascii?Q?R1VBYlFCaEFHa0FiQUJmQUdFQVpBQmtBSElBWlFCekFITUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQ3dBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFRQUFBQUFBQUFBQ0FBQUFBQUNlQUFBQWJRQmhBSElBZGdCbEFH?= =?us-ascii?Q?d0FiQUJmQUhRQVpRQnlBRzBBYVFCdUFIVUFjd0FBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= =?us-ascii?Q?QUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFBQUFB?= x-dg-rorf: true x-dg-reftwo: QUFBQUFBQUFBQUFCQUFBQUFBQUFBQUlBQUFBQUFBPT0iLz48L21ldGE+ x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: fd8f2679-f653-4fd4-33a1-08da8c4d526a x-ms-traffictypediagnostic: SJ0PR18MB4997:EE_ x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 8myfdUZkZLNh0U3uvAUwjMRtOBEdiD8yhZx9Q6UynTL0p45gkVEep5IiHvnSwGQlfwnXEh4L1zvqUl2pshb/Cxrrncm1pn92jJ6K4+QX1qUaNa2p8yAFtT8r9cfU/9xDLCdz2rDmxQ9Nc+rmMRTqCyDl8S5JFvRm/f5KuTw9R48yvW9ThLrBHtySGPYOHOOLkitF6LP1h3/r+QpLhaPvQ3bYiz3YYf2bZXgYMzO/Y826i/uSjzGFJaLRmyYJaz3osNVKnKPqU14vAvScxuuJrdIZ+CJ0QEJE72QTtT5rpWtXpVIqFQfQegh4jaUIo5hatSbFnFCcflOOmVDCn8W/lgafqpWnpMoMYQR3eeiKlhLxXbHVoqN2sTcOJKUj4uAVl1pAJz3Q12Fyf0zcWlQ6D7OXknSh1JSPoDfqcEl5Ta9T/8J0ocx3jZ6VYwwD4a33xr3lr0pS8hwDYncLSi99XtwibVhQIeIAo3Y2kbM1/Wj7kJMrx+7S/g/CzJC0k0g3GpmDRBCqgR8EwsU1VQJ80UoDZvtTu06nk6IWMhhRBHYXNMDE8tUwNO3FqDkZ3Mn5jIINfUyDHXHjXd4I4uL1CMpvIC/FeMq/17945+Ijs9zA5fbGpZK42w7DU4aXlfDFCmVB18kXfnb19vx9UMb1gjmzNL3GfYfnN03msnMxRz2iGybADDcLlcFWkeGMC7m1As7jDhG1ctXVDLEragw7BJGz6clBDnsUOR3NLqOcj7iYKCYWBvLlfG1Dkh/QO+qhgbbj7RWjAUIrVzVo3UnDXw== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:CO1PR18MB4732.namprd18.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230016)(4636009)(376002)(366004)(39860400002)(396003)(346002)(136003)(55016003)(5660300002)(478600001)(122000001)(66446008)(33656002)(8936002)(83380400001)(38070700005)(316002)(26005)(52536014)(9686003)(71200400001)(53546011)(76116006)(30864003)(6506007)(7696005)(66476007)(66946007)(66556008)(2906002)(4326008)(107886003)(186003)(8676002)(110136005)(86362001)(38100700002)(41300700001)(64756008)(54906003); DIR:OUT; SFP:1101; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?BwQnSrWesD8X7ArhJYlihw/GjRE6CS2cYyKrAgcdAw3pSpqkMK99SHbzhS8d?= =?us-ascii?Q?hzYBULrQLQ1L+kPSB2pmL5xw2OjFN8hSdZn0bCCm1VoK6Ivee03ggrENL4n6?= =?us-ascii?Q?Jq18xwlIHUdaQ3NBvi5gzkcoRFtoWuc6ZpFnVxiDryDcpwOfcxsR8ZKjW7dQ?= =?us-ascii?Q?yeQ+uqy+9wo9amfc/1Y7M32d7j1FBymZ/BxdCMKjH2/BzuD2INRkWoBpPMEz?= =?us-ascii?Q?eh1tCAS8os5hiJ2sCE9RwI+cKd7egqmdTK8aBa87j+5bQxFgg+dQXLMz9coI?= =?us-ascii?Q?XUsuGxVRLXMXyG7+HBcgc5Lq0TcJhtG9AVknfJFG42h44EzRyoBqNU52qA/g?= =?us-ascii?Q?Fqg+kkIQjabRLhnzG9z2Y3sePjSn5ShGgMzPr4q6OF5OTMDtGmE+ifPoppWR?= =?us-ascii?Q?Nwkg0VnOPYinX38EELNVb2Pzaup0ouTNpYREzuP3Dahe5HVaBcWH97gdWFc3?= =?us-ascii?Q?h3Szi7JyqiCprrC+3zGmwMVG16ZW1lN6edbxNS/L2PAOLOJ4BG4VwcRv2U0W?= =?us-ascii?Q?929H/VgHt7nS6P+ZzdHiEX/H+yDzBJnPwdSMj3RM0RaECg6CBxjkWHKjRtHJ?= =?us-ascii?Q?232UHfSpuy8hnzlJwFZR2Uo0l+PAotWy6va+lybOmkLMcFD8/TgS+XDYb+LO?= =?us-ascii?Q?XsxocHk13O3Q9izlyHb2LDDliC2br9lfhH8Dyf2890+yFYA44ZVsn/eVs8qP?= =?us-ascii?Q?kPcZH2GmP+cLKIbNk5BXz7371JCJrtXC2H60IniUCD+PANjkuNVOfUs+4z9o?= =?us-ascii?Q?i/dcScLp0jAWzIfl/2pvoNTyf2IEQ6xgLPuPGJE0ZTKx4WHD2fO9hgHjZjAi?= =?us-ascii?Q?xdZnRQcSlxqNrILNElY4TZawaCN6yEYTJ0qnXrdwdc0vULEKhyBUIkWe7GSZ?= =?us-ascii?Q?bdUrLphLeV26ZutgrmzMLGIBOVVCl2SErgi9KzItiE2QseMNw0NGGWc7P1Qi?= =?us-ascii?Q?D21Poars3nYGrVL24JTA0r6v4hbdskwr6WVE4VwWufUAcjqyQSr1bawUzc6r?= =?us-ascii?Q?WAIy/xlLs82Kd7ia6oZwwceGaUTJ+zHzLfjyfApEjIVcVFbgVDoVyk0M0/3D?= =?us-ascii?Q?y8guVeTEc6ZkH65dps9H5fLJT9/2950Qb67bFKq2EvWYTU6sXiuDfDi0vj18?= =?us-ascii?Q?TtndTgct5lXUAfza0GpBAYHCWdt7lN3IL313ZcrdOJIL9XD4LmxzHvHEJgIL?= =?us-ascii?Q?f+yOsWBIsqsnYrsxTOeKauV0Q5xx3o1NPCVNeZy6fcytRf7Mjqa4ICJ8rZuU?= =?us-ascii?Q?/gGiGqx+73iqj5dIcVpxG/B9pD5o0+Tm3CHnwj7U2ed9v8fUo4zjq6M9zYJj?= =?us-ascii?Q?cTxYxuiUI3P++XGZzqViwoLfSJfFhxs9yzodGvsrqhy3yWOKUuFcQ6GV0fMc?= =?us-ascii?Q?E/93NQRxWW/jvTImLfjnDhLZevkJl2BzOhb3sif7E9X7nuUnA8p9pIS3wmBX?= =?us-ascii?Q?alT0rnsQw5Svw1tgfRWPSmPlwj5DOL/iMwucapFWbOI3Y3qDv9T9y/YIgu4K?= =?us-ascii?Q?pPI6CuP7JwFoKGNXGPi9DIl+utCWJxXg0s7FM61Zp3rN3yOALfD2l/dkW3NN?= =?us-ascii?Q?aMU/uzyLZkFPxQT03abIQxKi6gLeJEPJ4MM69Rcs?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO1PR18MB4732.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: fd8f2679-f653-4fd4-33a1-08da8c4d526a X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Sep 2022 19:08:14.8854 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: hn4uA3llfw89w40i96Kyn47NP1vh6ibhnPEOyGhoKBJhbIzzVuHgJAa6TdPG+eVVViw7GWc9+DpYn4JA9N55Bw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR18MB4997 X-Proofpoint-GUID: HM6HReHU0ayPvkOiyVZQpdteU6IgKWIy X-Proofpoint-ORIG-GUID: HM6HReHU0ayPvkOiyVZQpdteU6IgKWIy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-09-01_12,2022-08-31_03,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Radha Mohan Chintakuntla > Sent: Friday, August 5, 2022 12:30 PM > To: dev@dpdk.org > Cc: thomas@monjalon.net; Radha Chintakuntla ; Nithin > Kumar Dabilpuram ; Kiran Kumar Kokkilagadda > ; Sunil Kumar Kori ; Satha > Koteswara Rao Kottidi ; Veerasenareddy Burru > > Subject: [PATCH v3] dma/cnxk: add support for CN10K DMA engine >=20 > Added support for CN10K SoC DMA engine to dmadev. >=20 > Signed-off-by: Radha Mohan Chintakuntla > Reviewed-by: Jerin Jacob Kollanukkaran > --- > Changes from v2: > - Added missing files required in the patch >=20 > Changes from v1: > - Removed gerrit changeID >=20 > drivers/common/cnxk/hw/dpi.h | 16 +- > drivers/common/cnxk/roc_dpi_priv.h | 2 +- > drivers/dma/cnxk/cnxk_dmadev.c | 248 +++++++++++++++++++++++++---- > drivers/dma/cnxk/cnxk_dmadev.h | 2 +- > 4 files changed, 225 insertions(+), 43 deletions(-) >=20 > diff --git a/drivers/common/cnxk/hw/dpi.h b/drivers/common/cnxk/hw/dpi.h > index 2da123228f..a34713dde6 100644 > --- a/drivers/common/cnxk/hw/dpi.h > +++ b/drivers/common/cnxk/hw/dpi.h > @@ -61,7 +61,7 @@ > */ > union dpi_instr_hdr_s { > uint64_t u[4]; > - struct dpi_dma_instr_hdr_s_s { > + struct dpi_cn9k_instr_hdr_s_s { > uint64_t tag : 32; > uint64_t tt : 2; > uint64_t grp : 10; > @@ -93,17 +93,9 @@ union dpi_instr_hdr_s { > /* Word 2 - End */ > uint64_t reserved_192_255 : 64; > /* Word 3 - End */ > - } s; > -}; > + } cn9k; >=20 > -/** > - * Structure dpi_cn10k_instr_hdr_s for CN10K > - * > - * DPI DMA Instruction Header Format > - */ > -union dpi_cn10k_instr_hdr_s { > - uint64_t u[4]; > - struct dpi_cn10k_dma_instr_hdr_s_s { > + struct dpi_cn10k_instr_hdr_s_s { > uint64_t nfst : 4; > uint64_t reserved_4_5 : 2; > uint64_t nlst : 4; > @@ -135,7 +127,7 @@ union dpi_cn10k_instr_hdr_s { > /* Word 2 - End */ > uint64_t reserved_192_255 : 64; > /* Word 3 - End */ > - } s; > + } cn10k; > }; >=20 > #endif /*__DEV_DPI_HW_H__*/ > diff --git a/drivers/common/cnxk/roc_dpi_priv.h > b/drivers/common/cnxk/roc_dpi_priv.h > index 92953fbcfc..1fa1a715d3 100644 > --- a/drivers/common/cnxk/roc_dpi_priv.h > +++ b/drivers/common/cnxk/roc_dpi_priv.h > @@ -23,7 +23,7 @@ typedef union dpi_mbox_msg_t { > uint64_t u[2]; > struct dpi_mbox_message_s { > /* VF ID to configure */ > - uint64_t vfid : 4; > + uint64_t vfid : 8; > /* Command code */ > uint64_t cmd : 4; > /* Command buffer size in 8-byte words */ diff --git > a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c index > 2824c1b44f..a67bcba9d4 100644 > --- a/drivers/dma/cnxk/cnxk_dmadev.c > +++ b/drivers/dma/cnxk/cnxk_dmadev.c > @@ -70,31 +70,31 @@ cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, > uint16_t vchan, > RTE_SET_USED(vchan); > RTE_SET_USED(conf_sz); >=20 > - header->s.pt =3D DPI_HDR_PT_ZBW_CA; > + header->cn9k.pt =3D DPI_HDR_PT_ZBW_CA; >=20 > switch (conf->direction) { > case RTE_DMA_DIR_DEV_TO_MEM: > - header->s.xtype =3D DPI_XTYPE_INBOUND; > - header->s.lport =3D conf->src_port.pcie.coreid; > - header->s.fport =3D 0; > - header->s.pvfe =3D 1; > + header->cn9k.xtype =3D DPI_XTYPE_INBOUND; > + header->cn9k.lport =3D conf->src_port.pcie.coreid; > + header->cn9k.fport =3D 0; > + header->cn9k.pvfe =3D 1; > break; > case RTE_DMA_DIR_MEM_TO_DEV: > - header->s.xtype =3D DPI_XTYPE_OUTBOUND; > - header->s.lport =3D 0; > - header->s.fport =3D conf->dst_port.pcie.coreid; > - header->s.pvfe =3D 1; > + header->cn9k.xtype =3D DPI_XTYPE_OUTBOUND; > + header->cn9k.lport =3D 0; > + header->cn9k.fport =3D conf->dst_port.pcie.coreid; > + header->cn9k.pvfe =3D 1; > break; > case RTE_DMA_DIR_MEM_TO_MEM: > - header->s.xtype =3D DPI_XTYPE_INTERNAL_ONLY; > - header->s.lport =3D 0; > - header->s.fport =3D 0; > - header->s.pvfe =3D 0; > + header->cn9k.xtype =3D DPI_XTYPE_INTERNAL_ONLY; > + header->cn9k.lport =3D 0; > + header->cn9k.fport =3D 0; > + header->cn9k.pvfe =3D 0; > break; > case RTE_DMA_DIR_DEV_TO_DEV: > - header->s.xtype =3D DPI_XTYPE_EXTERNAL_ONLY; > - header->s.lport =3D conf->src_port.pcie.coreid; > - header->s.fport =3D conf->dst_port.pcie.coreid; > + header->cn9k.xtype =3D DPI_XTYPE_EXTERNAL_ONLY; > + header->cn9k.lport =3D conf->src_port.pcie.coreid; > + header->cn9k.fport =3D conf->dst_port.pcie.coreid; > }; >=20 > for (i =3D 0; i < conf->nb_desc; i++) { > @@ -103,6 +103,63 @@ cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, > uint16_t vchan, > plt_err("Failed to allocate for comp_data"); > return -ENOMEM; > } > + comp_data->cdata =3D DPI_REQ_CDATA; > + dpivf->conf.c_desc.compl_ptr[i] =3D comp_data; > + }; > + dpivf->conf.c_desc.max_cnt =3D DPI_MAX_DESC; > + dpivf->conf.c_desc.head =3D 0; > + dpivf->conf.c_desc.tail =3D 0; > + > + return 0; > +} > + > +static int > +cn10k_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan, > + const struct rte_dma_vchan_conf *conf, > + uint32_t conf_sz) > +{ > + struct cnxk_dpi_vf_s *dpivf =3D dev->fp_obj->dev_private; > + struct cnxk_dpi_compl_s *comp_data; > + union dpi_instr_hdr_s *header =3D &dpivf->conf.hdr; > + int i; > + > + RTE_SET_USED(vchan); > + RTE_SET_USED(conf_sz); > + > + header->cn10k.pt =3D DPI_HDR_PT_ZBW_CA; > + > + switch (conf->direction) { > + case RTE_DMA_DIR_DEV_TO_MEM: > + header->cn10k.xtype =3D DPI_XTYPE_INBOUND; > + header->cn10k.lport =3D conf->src_port.pcie.coreid; > + header->cn10k.fport =3D 0; > + header->cn10k.pvfe =3D 1; > + break; > + case RTE_DMA_DIR_MEM_TO_DEV: > + header->cn10k.xtype =3D DPI_XTYPE_OUTBOUND; > + header->cn10k.lport =3D 0; > + header->cn10k.fport =3D conf->dst_port.pcie.coreid; > + header->cn10k.pvfe =3D 1; > + break; > + case RTE_DMA_DIR_MEM_TO_MEM: > + header->cn10k.xtype =3D DPI_XTYPE_INTERNAL_ONLY; > + header->cn10k.lport =3D 0; > + header->cn10k.fport =3D 0; > + header->cn10k.pvfe =3D 0; > + break; > + case RTE_DMA_DIR_DEV_TO_DEV: > + header->cn10k.xtype =3D DPI_XTYPE_EXTERNAL_ONLY; > + header->cn10k.lport =3D conf->src_port.pcie.coreid; > + header->cn10k.fport =3D conf->dst_port.pcie.coreid; > + }; > + > + for (i =3D 0; i < conf->nb_desc; i++) { > + comp_data =3D rte_zmalloc(NULL, sizeof(*comp_data), 0); > + if (comp_data =3D=3D NULL) { > + plt_err("Failed to allocate for comp_data"); > + return -ENOMEM; > + } > + comp_data->cdata =3D DPI_REQ_CDATA; > dpivf->conf.c_desc.compl_ptr[i] =3D comp_data; > }; > dpivf->conf.c_desc.max_cnt =3D DPI_MAX_DESC; @@ -237,17 +294,17 > @@ cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src, >=20 > comp_ptr =3D dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail]; > comp_ptr->cdata =3D DPI_REQ_CDATA; > - header->s.ptr =3D (uint64_t)comp_ptr; > + header->cn9k.ptr =3D (uint64_t)comp_ptr; > STRM_INC(dpivf->conf.c_desc); >=20 > - header->s.nfst =3D 1; > - header->s.nlst =3D 1; > + header->cn9k.nfst =3D 1; > + header->cn9k.nlst =3D 1; >=20 > /* > * For inbound case, src pointers are last pointers. > * For all other cases, src pointers are first pointers. > */ > - if (header->s.xtype =3D=3D DPI_XTYPE_INBOUND) { > + if (header->cn9k.xtype =3D=3D DPI_XTYPE_INBOUND) { > fptr =3D dst; > lptr =3D src; > } else { > @@ -296,21 +353,21 @@ cnxk_dmadev_copy_sg(void *dev_private, uint16_t > vchan, >=20 > comp_ptr =3D dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail]; > comp_ptr->cdata =3D DPI_REQ_CDATA; > - header->s.ptr =3D (uint64_t)comp_ptr; > + header->cn9k.ptr =3D (uint64_t)comp_ptr; > STRM_INC(dpivf->conf.c_desc); >=20 > /* > * For inbound case, src pointers are last pointers. > * For all other cases, src pointers are first pointers. > */ > - if (header->s.xtype =3D=3D DPI_XTYPE_INBOUND) { > - header->s.nfst =3D nb_dst & 0xf; > - header->s.nlst =3D nb_src & 0xf; > + if (header->cn9k.xtype =3D=3D DPI_XTYPE_INBOUND) { > + header->cn9k.nfst =3D nb_dst & 0xf; > + header->cn9k.nlst =3D nb_src & 0xf; > fptr =3D &dst[0]; > lptr =3D &src[0]; > } else { > - header->s.nfst =3D nb_src & 0xf; > - header->s.nlst =3D nb_dst & 0xf; > + header->cn9k.nfst =3D nb_src & 0xf; > + header->cn9k.nlst =3D nb_dst & 0xf; > fptr =3D &src[0]; > lptr =3D &dst[0]; > } > @@ -319,13 +376,13 @@ cnxk_dmadev_copy_sg(void *dev_private, uint16_t > vchan, > dpivf->cmd[1] =3D header->u[1]; > dpivf->cmd[2] =3D header->u[2]; > num_words +=3D 4; > - for (i =3D 0; i < header->s.nfst; i++) { > + for (i =3D 0; i < header->cn9k.nfst; i++) { > dpivf->cmd[num_words++] =3D (uint64_t)fptr->length; > dpivf->cmd[num_words++] =3D fptr->addr; > fptr++; > } >=20 > - for (i =3D 0; i < header->s.nlst; i++) { > + for (i =3D 0; i < header->cn9k.nlst; i++) { > dpivf->cmd[num_words++] =3D (uint64_t)lptr->length; > dpivf->cmd[num_words++] =3D lptr->addr; > lptr++; > @@ -342,9 +399,113 @@ cnxk_dmadev_copy_sg(void *dev_private, uint16_t > vchan, > dpivf->num_words +=3D num_words; > } >=20 > + return (rc < 0) ? rc : dpivf->desc_idx++; } > + > +static int > +cn10k_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src, > + rte_iova_t dst, uint32_t length, uint64_t flags) { > + struct cnxk_dpi_vf_s *dpivf =3D dev_private; > + union dpi_instr_hdr_s *header =3D &dpivf->conf.hdr; > + struct cnxk_dpi_compl_s *comp_ptr; > + rte_iova_t fptr, lptr; > + int num_words =3D 0; > + int rc; > + > + RTE_SET_USED(vchan); > + > + comp_ptr =3D dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail]; > + comp_ptr->cdata =3D DPI_REQ_CDATA; > + header->cn10k.ptr =3D (uint64_t)comp_ptr; > + STRM_INC(dpivf->conf.c_desc); > + > + header->cn10k.nfst =3D 1; > + header->cn10k.nlst =3D 1; > + > + fptr =3D src; > + lptr =3D dst; > + > + dpivf->cmd[0] =3D header->u[0]; > + dpivf->cmd[1] =3D header->u[1]; > + dpivf->cmd[2] =3D header->u[2]; > + /* word3 is always 0 */ > + num_words +=3D 4; > + dpivf->cmd[num_words++] =3D length; > + dpivf->cmd[num_words++] =3D fptr; > + dpivf->cmd[num_words++] =3D length; > + dpivf->cmd[num_words++] =3D lptr; > + > + rc =3D __dpi_queue_write(&dpivf->rdpi, dpivf->cmd, num_words); > + if (!rc) { > + if (flags & RTE_DMA_OP_FLAG_SUBMIT) { > + rte_wmb(); > + plt_write64(num_words, > + dpivf->rdpi.rbase + DPI_VDMA_DBELL); > + dpivf->stats.submitted++; > + } > + dpivf->num_words +=3D num_words; > + } > + > return dpivf->desc_idx++; > } >=20 > +static int > +cn10k_dmadev_copy_sg(void *dev_private, uint16_t vchan, > + const struct rte_dma_sge *src, > + const struct rte_dma_sge *dst, uint16_t nb_src, > + uint16_t nb_dst, uint64_t flags) { > + struct cnxk_dpi_vf_s *dpivf =3D dev_private; > + union dpi_instr_hdr_s *header =3D &dpivf->conf.hdr; > + const struct rte_dma_sge *fptr, *lptr; > + struct cnxk_dpi_compl_s *comp_ptr; > + int num_words =3D 0; > + int i, rc; > + > + RTE_SET_USED(vchan); > + > + comp_ptr =3D dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail]; > + comp_ptr->cdata =3D DPI_REQ_CDATA; > + header->cn10k.ptr =3D (uint64_t)comp_ptr; > + STRM_INC(dpivf->conf.c_desc); > + > + header->cn10k.nfst =3D nb_src & 0xf; > + header->cn10k.nlst =3D nb_dst & 0xf; > + fptr =3D &src[0]; > + lptr =3D &dst[0]; > + > + dpivf->cmd[0] =3D header->u[0]; > + dpivf->cmd[1] =3D header->u[1]; > + dpivf->cmd[2] =3D header->u[2]; > + num_words +=3D 4; > + > + for (i =3D 0; i < header->cn10k.nfst; i++) { > + dpivf->cmd[num_words++] =3D (uint64_t)fptr->length; > + dpivf->cmd[num_words++] =3D fptr->addr; > + fptr++; > + } > + > + for (i =3D 0; i < header->cn10k.nlst; i++) { > + dpivf->cmd[num_words++] =3D (uint64_t)lptr->length; > + dpivf->cmd[num_words++] =3D lptr->addr; > + lptr++; > + } > + > + rc =3D __dpi_queue_write(&dpivf->rdpi, dpivf->cmd, num_words); > + if (!rc) { > + if (flags & RTE_DMA_OP_FLAG_SUBMIT) { > + rte_wmb(); > + plt_write64(num_words, > + dpivf->rdpi.rbase + DPI_VDMA_DBELL); > + dpivf->stats.submitted +=3D nb_src; > + } > + dpivf->num_words +=3D num_words; > + } > + > + return (rc < 0) ? rc : dpivf->desc_idx++; } > + > static uint16_t > cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t > nb_cpls, > uint16_t *last_idx, bool *has_error) @@ -353,11 +514,17 > @@ cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const > uint16_t nb_cpls, > int cnt; >=20 > RTE_SET_USED(vchan); > + > + if (dpivf->stats.submitted =3D=3D dpivf->stats.completed) > + return 0; > + > for (cnt =3D 0; cnt < nb_cpls; cnt++) { > struct cnxk_dpi_compl_s *comp_ptr =3D > dpivf->conf.c_desc.compl_ptr[cnt]; >=20 > if (comp_ptr->cdata) { > + if (comp_ptr->cdata =3D=3D DPI_REQ_CDATA) > + break; > *has_error =3D 1; > dpivf->stats.errors++; > break; > @@ -385,8 +552,12 @@ cnxk_dmadev_completed_status(void *dev_private, > uint16_t vchan, > struct cnxk_dpi_compl_s *comp_ptr =3D > dpivf->conf.c_desc.compl_ptr[cnt]; > status[cnt] =3D comp_ptr->cdata; > - if (comp_ptr->cdata) > + if (status[cnt]) { > + if (status[cnt] =3D=3D DPI_REQ_CDATA) > + break; > + > dpivf->stats.errors++; > + } > } >=20 > *last_idx =3D cnt - 1; > @@ -435,6 +606,17 @@ cnxk_stats_reset(struct rte_dma_dev *dev, uint16_t > vchan __rte_unused) > return 0; > } >=20 > +static const struct rte_dma_dev_ops cn10k_dmadev_ops =3D { > + .dev_close =3D cnxk_dmadev_close, > + .dev_configure =3D cnxk_dmadev_configure, > + .dev_info_get =3D cnxk_dmadev_info_get, > + .dev_start =3D cnxk_dmadev_start, > + .dev_stop =3D cnxk_dmadev_stop, > + .stats_get =3D cnxk_stats_get, > + .stats_reset =3D cnxk_stats_reset, > + .vchan_setup =3D cn10k_dmadev_vchan_setup, }; > + > static const struct rte_dma_dev_ops cnxk_dmadev_ops =3D { > .dev_close =3D cnxk_dmadev_close, > .dev_configure =3D cnxk_dmadev_configure, @@ -486,6 +668,14 @@ > cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused, > dmadev->fp_obj->completed =3D cnxk_dmadev_completed; > dmadev->fp_obj->completed_status =3D > cnxk_dmadev_completed_status; >=20 > + if (pci_dev->id.subsystem_device_id =3D=3D > PCI_SUBSYSTEM_DEVID_CN10KA || > + pci_dev->id.subsystem_device_id =3D=3D > PCI_SUBSYSTEM_DEVID_CNF10KA || > + pci_dev->id.subsystem_device_id =3D=3D > PCI_SUBSYSTEM_DEVID_CN10KB) { > + dmadev->dev_ops =3D &cn10k_dmadev_ops; > + dmadev->fp_obj->copy =3D cn10k_dmadev_copy; > + dmadev->fp_obj->copy_sg =3D cn10k_dmadev_copy_sg; > + } > + > rdpi =3D &dpivf->rdpi; >=20 > rdpi->pci_dev =3D pci_dev; > diff --git a/drivers/dma/cnxk/cnxk_dmadev.h > b/drivers/dma/cnxk/cnxk_dmadev.h index 5fc241b55e..e1f5694f50 100644 > --- a/drivers/dma/cnxk/cnxk_dmadev.h > +++ b/drivers/dma/cnxk/cnxk_dmadev.h > @@ -8,7 +8,7 @@ > #define DPI_QUEUE_STOP 0x0 > #define DPI_QUEUE_START 0x1 > #define STRM_INC(s) ((s).tail =3D ((s).tail + 1) % (s).max_cnt) > -#define DPI_MAX_DESC DPI_MAX_POINTER > +#define DPI_MAX_DESC 1024 >=20 > /* Set Completion data to 0xFF when request submitted, > * upon successful request completion engine reset to completion status > -- > 2.17.1 Hi Thomas, Could you please pick this patch for main ? Regards, Radha