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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO6PR12MB5396.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7ceda080-1d45-4adb-0a57-08dc30f6dc28 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Feb 2024 02:59:59.3064 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Rca/taMlhjzFK3RKBIYxmck8eQZi0cpqM4g+IiJwAkoIuCijscQutzcY1TWZjMoABRaVfkw9oqLPfnCFFYqMEQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5339 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Hi, > -----Original Message----- > From: Michael Baum > Sent: Wednesday, February 14, 2024 3:30 PM > To: dev@dpdk.org > Cc: Matan Azrad ; Dariusz Sosnowski > ; Raslan Darawsheh ; Slava > Ovsiienko ; Ori Kam ; Suanming > Mou > Subject: [PATCH v5 3/3] net/mlx5/hws: add compare ESP sequence number > support >=20 > Add support for compare item with "RTE_FLOW_FIELD_ESP_SEQ_NUM" field. Small comment, please don't forget to add the new supported comparison fiel= d to rel_notes. >=20 > Signed-off-by: Michael Baum Acked-by: Suanming Mou > --- > doc/guides/nics/mlx5.rst | 1 + > drivers/net/mlx5/hws/mlx5dr_definer.c | 22 ++++++++++++++++++++-- > drivers/net/mlx5/mlx5_flow_hw.c | 3 +++ > 3 files changed, 24 insertions(+), 2 deletions(-) >=20 > diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index > 43ef8a99dc..b793f1ef58 100644 > --- a/doc/guides/nics/mlx5.rst > +++ b/doc/guides/nics/mlx5.rst > @@ -823,6 +823,7 @@ Limitations > - Only single item is supported per pattern template. > - Only 32-bit comparison is supported or 16-bits for random field. > - Only supported for ``RTE_FLOW_FIELD_META``, ``RTE_FLOW_FIELD_TAG``, > + ``RTE_FLOW_FIELD_ESP_SEQ_NUM``, > ``RTE_FLOW_FIELD_RANDOM`` and ``RTE_FLOW_FIELD_VALUE``. > - The field type ``RTE_FLOW_FIELD_VALUE`` must be the base (``b``) fie= ld. > - The field type ``RTE_FLOW_FIELD_RANDOM`` can only be compared with d= iff > --git a/drivers/net/mlx5/hws/mlx5dr_definer.c > b/drivers/net/mlx5/hws/mlx5dr_definer.c > index 2d86175ca2..b29d7451e7 100644 > --- a/drivers/net/mlx5/hws/mlx5dr_definer.c > +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c > @@ -396,10 +396,20 @@ mlx5dr_definer_compare_base_value_set(const void > *item_spec, >=20 > value =3D (const uint32_t *)&b->value[0]; >=20 > - if (a->field =3D=3D RTE_FLOW_FIELD_RANDOM) > + switch (a->field) { > + case RTE_FLOW_FIELD_RANDOM: > *base =3D htobe32(*value << 16); > - else > + break; > + case RTE_FLOW_FIELD_TAG: > + case RTE_FLOW_FIELD_META: > *base =3D htobe32(*value); > + break; > + case RTE_FLOW_FIELD_ESP_SEQ_NUM: > + *base =3D *value; > + break; > + default: > + break; > + } >=20 > MLX5_SET(ste_match_4dw_range_ctrl_dw, ctrl, base0, 1); } @@ -2887,6 > +2897,14 @@ mlx5dr_definer_conv_item_compare_field(const struct > rte_flow_field_data *f, > fc->compare_idx =3D dw_offset; > DR_CALC_SET_HDR(fc, random_number, random_number); > break; > + case RTE_FLOW_FIELD_ESP_SEQ_NUM: > + fc =3D &cd- > >fc[MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER]; > + fc->item_idx =3D item_idx; > + fc->tag_set =3D &mlx5dr_definer_compare_set; > + fc->tag_mask_set =3D &mlx5dr_definer_ones_set; > + fc->compare_idx =3D dw_offset; > + DR_CALC_SET_HDR(fc, ipsec, sequence_number); > + break; > default: > DR_LOG(ERR, "%u field is not supported", f->field); > goto err_notsup; > diff --git a/drivers/net/mlx5/mlx5_flow_hw.c > b/drivers/net/mlx5/mlx5_flow_hw.c index b5741f0817..4d6fb489b2 100644 > --- a/drivers/net/mlx5/mlx5_flow_hw.c > +++ b/drivers/net/mlx5/mlx5_flow_hw.c > @@ -6725,6 +6725,7 @@ flow_hw_item_compare_field_validate(enum > rte_flow_field_id arg_field, > switch (arg_field) { > case RTE_FLOW_FIELD_TAG: > case RTE_FLOW_FIELD_META: > + case RTE_FLOW_FIELD_ESP_SEQ_NUM: > break; > case RTE_FLOW_FIELD_RANDOM: > if (base_field =3D=3D RTE_FLOW_FIELD_VALUE) @@ -6743,6 +6744,7 > @@ flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field, > case RTE_FLOW_FIELD_TAG: > case RTE_FLOW_FIELD_META: > case RTE_FLOW_FIELD_VALUE: > + case RTE_FLOW_FIELD_ESP_SEQ_NUM: > break; > default: > return rte_flow_error_set(error, ENOTSUP, @@ -6759,6 +6761,7 > @@ flow_hw_item_compare_width_supported(enum rte_flow_field_id field) > switch (field) { > case RTE_FLOW_FIELD_TAG: > case RTE_FLOW_FIELD_META: > + case RTE_FLOW_FIELD_ESP_SEQ_NUM: > return 32; > case RTE_FLOW_FIELD_RANDOM: > return 16; > -- > 2.25.1