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x-ms-exchange-antispam-messagedata: =?us-ascii?Q?BrdkALxKx9zH085rVYQLiwOnWVb7nlukzrfScRoDmjrYuvLlcguegXoiD1zC?= =?us-ascii?Q?paZc0t9V4dgicewDu32JFjOAo0xYsXvlJXhosAKr6VcNDLWKaMT7X0CiE0iX?= =?us-ascii?Q?ntTqrKmf1AommYVjnvxBFMftOPoN8rsvmoYrs2mofMFy4P6hbxCDlmBs+9SN?= =?us-ascii?Q?d6kEwgeJtSobTps/rubR1H+uHPVS32FA+wDMAOl0JSdDzp5Ty16ilYWJxFjx?= =?us-ascii?Q?nELk5Ot4XRPnXJfDddvHBFdoX/24wpk0iS1mU6ZtwkufrFqxOsPAatxCPv3D?= =?us-ascii?Q?Cf00J8okZbfTOhp2Kcw1L3jby1wIiyB2wqSILlrvRQ/AGxzgn+AcW7l+8xsZ?= =?us-ascii?Q?j1ZNsaCe3oembYr0RSQirtYVnE+sap8unocJqpf/VFi/hAvfShBGqt4SelGl?= =?us-ascii?Q?enKOjQBYb9/SnDxkelhs8J7SZAzOa1yJmDfzq5wp4/XBKhGDnc6J6H5NDJSO?= =?us-ascii?Q?B7ENKRSZhJN0dxA4rnY1nYdPKRvAlFw+0RdyAVDHpJcrAmntB1zUXtbIVrGQ?= =?us-ascii?Q?2+0bhzsiS3EOlnxh/lFZBotca/H7i+5EgvOYAI5XKd+nYH7rHtUqdPgqf+yr?= =?us-ascii?Q?lf6Jg7ktS9FeYMSqumNYmkNJ+NPYENFwfcaqDSpqrWwEcE3WRemaB//BBQZO?= =?us-ascii?Q?DSUAtaZaqeBYXkDuRfOnpoRuQVvl3+ghwZFu3fKfkrwpl2ccIS1Yh5cAInpl?= =?us-ascii?Q?ycjsnQTzXjddoSZdFKtYkTmvH9ERLv6idkPGt7WoQmeAvhEP9L5bqf/GvgCF?= =?us-ascii?Q?mTiBNtuXz2AbcdhjZWeE1XQsCZlswtO0qZmxTSY4IO7x2cDyeHfleNjiEXVR?= =?us-ascii?Q?3hOTWxr15+Rjrygd9aILA1ZcjZORO7bH06+EyzBjMjhLk9UtNYnGivLA3SdC?= =?us-ascii?Q?9At+3KVk8HUWyydcUj6csHB1QD+52Kl2YKTDPFKrvl5fPwYGBKEgbOCNx5bV?= =?us-ascii?Q?HNyo2NSmfhUlxzKkOusYTGKd6nLFrROb1/uOPt85gE4=3D?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO6PR18MB3828.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 886176bc-3a28-4c25-80e1-08d8a664fbf5 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Dec 2020 10:33:12.5612 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: LCVVRdIMDP+oEHJliAUUkJgW4n33YfOZsEqoNRGjxhiEr8W6n3ZWYSOS7GSS18CojS70mddodMeNAmWfFL/2xk+dU1irGAYm5wQSxyETnHo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR18MB3860 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2020-12-22_04:2020-12-21, 2020-12-22 signatures=0 Subject: Re: [dpdk-dev] [RFC PATCH v1 4/6] app/eventdev: add release barriers for pipeline test X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >Add release barriers before updating the processed packets for worker >lcores to ensure the worker lcore has really finished data processing >and then it can update the processed packets number. > I believe we can live with minor inaccuracies in stats being presented as atomics are pretty heavy when scheduler is limited to burst size as 1.=20 One option is to move it before a pipeline operation (pipeline_event_tx, pi= peline_fwd_event etc.) as they imply implicit release barrier (as all the changes done to the even= t should be visible to the next core). >Fixes: 314bcf58ca8f ("app/eventdev: add pipeline queue worker >functions") >Cc: pbhagavatula@marvell.com >Cc: stable@dpdk.org > >Signed-off-by: Phil Yang >Signed-off-by: Feifei Wang >Reviewed-by: Ruifeng Wang >--- > app/test-eventdev/test_pipeline_queue.c | 64 >+++++++++++++++++++++---- > 1 file changed, 56 insertions(+), 8 deletions(-) > >diff --git a/app/test-eventdev/test_pipeline_queue.c b/app/test- >eventdev/test_pipeline_queue.c >index 7bebac34f..0c0ec0ceb 100644 >--- a/app/test-eventdev/test_pipeline_queue.c >+++ b/app/test-eventdev/test_pipeline_queue.c >@@ -30,7 +30,13 @@ pipeline_queue_worker_single_stage_tx(void >*arg) > > if (ev.sched_type =3D=3D RTE_SCHED_TYPE_ATOMIC) { > pipeline_event_tx(dev, port, &ev); >- w->processed_pkts++; >+ >+ /* release barrier here ensures stored operation >+ * of the event completes before the number of >+ * processed pkts is visible to the main core >+ */ >+ __atomic_fetch_add(&(w->processed_pkts), 1, >+ __ATOMIC_RELEASE); > } else { > ev.queue_id++; > pipeline_fwd_event(&ev, >RTE_SCHED_TYPE_ATOMIC); >@@ -59,7 +65,13 @@ pipeline_queue_worker_single_stage_fwd(void >*arg) > rte_event_eth_tx_adapter_txq_set(ev.mbuf, 0); > pipeline_fwd_event(&ev, RTE_SCHED_TYPE_ATOMIC); > pipeline_event_enqueue(dev, port, &ev); >- w->processed_pkts++; >+ >+ /* release barrier here ensures stored operation >+ * of the event completes before the number of >+ * processed pkts is visible to the main core >+ */ >+ __atomic_fetch_add(&(w->processed_pkts), 1, >+ __ATOMIC_RELEASE); > } > > return 0; >@@ -84,7 +96,13 @@ >pipeline_queue_worker_single_stage_burst_tx(void *arg) > if (ev[i].sched_type =3D=3D >RTE_SCHED_TYPE_ATOMIC) { > pipeline_event_tx(dev, port, &ev[i]); > ev[i].op =3D RTE_EVENT_OP_RELEASE; >- w->processed_pkts++; >+ >+ /* release barrier here ensures stored >operation >+ * of the event completes before the >number of >+ * processed pkts is visible to the main >core >+ */ >+ __atomic_fetch_add(&(w- >>processed_pkts), 1, >+ __ATOMIC_RELEASE); > } else { > ev[i].queue_id++; > pipeline_fwd_event(&ev[i], >@@ -121,7 +139,13 @@ >pipeline_queue_worker_single_stage_burst_fwd(void *arg) > } > > pipeline_event_enqueue_burst(dev, port, ev, nb_rx); >- w->processed_pkts +=3D nb_rx; >+ >+ /* release barrier here ensures stored operation >+ * of the event completes before the number of >+ * processed pkts is visible to the main core >+ */ >+ __atomic_fetch_add(&(w->processed_pkts), nb_rx, >+ __ATOMIC_RELEASE); > } > > return 0; >@@ -146,7 +170,13 @@ pipeline_queue_worker_multi_stage_tx(void >*arg) > > if (ev.queue_id =3D=3D tx_queue[ev.mbuf->port]) { > pipeline_event_tx(dev, port, &ev); >- w->processed_pkts++; >+ >+ /* release barrier here ensures stored operation >+ * of the event completes before the number of >+ * processed pkts is visible to the main core >+ */ >+ __atomic_fetch_add(&(w->processed_pkts), 1, >+ __ATOMIC_RELEASE); > continue; > } > >@@ -180,7 +210,13 @@ >pipeline_queue_worker_multi_stage_fwd(void *arg) > ev.queue_id =3D tx_queue[ev.mbuf->port]; > rte_event_eth_tx_adapter_txq_set(ev.mbuf, 0); > pipeline_fwd_event(&ev, >RTE_SCHED_TYPE_ATOMIC); >- w->processed_pkts++; >+ >+ /* release barrier here ensures stored operation >+ * of the event completes before the number of >+ * processed pkts is visible to the main core >+ */ >+ __atomic_fetch_add(&(w->processed_pkts), 1, >+ __ATOMIC_RELEASE); > } else { > ev.queue_id++; > pipeline_fwd_event(&ev, >sched_type_list[cq_id]); >@@ -214,7 +250,13 @@ >pipeline_queue_worker_multi_stage_burst_tx(void *arg) > if (ev[i].queue_id =3D=3D tx_queue[ev[i].mbuf- >>port]) { > pipeline_event_tx(dev, port, &ev[i]); > ev[i].op =3D RTE_EVENT_OP_RELEASE; >- w->processed_pkts++; >+ >+ /* release barrier here ensures stored >operation >+ * of the event completes before the >number of >+ * processed pkts is visible to the main >core >+ */ >+ __atomic_fetch_add(&(w- >>processed_pkts), 1, >+ __ATOMIC_RELEASE); > continue; > } > >@@ -254,7 +296,13 @@ >pipeline_queue_worker_multi_stage_burst_fwd(void *arg) > > rte_event_eth_tx_adapter_txq_set(ev[i].mbuf, 0); > pipeline_fwd_event(&ev[i], > > RTE_SCHED_TYPE_ATOMIC); >- w->processed_pkts++; >+ >+ /* release barrier here ensures stored >operation >+ * of the event completes before the >number of >+ * processed pkts is visible to the main >core >+ */ >+ __atomic_fetch_add(&(w- >>processed_pkts), 1, >+ __ATOMIC_RELEASE); > } else { > ev[i].queue_id++; > pipeline_fwd_event(&ev[i], >-- >2.17.1