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Wed, 18 May 2022 09:18:08 +0000 From: Rahul Bhansali To: =?iso-8859-2?Q?Juraj_Linke=B9?= , "dev@dpdk.org" , Ruifeng Wang , Jan Viktorin , Bruce Richardson CC: Jerin Jacob Kollanukkaran Subject: RE: [PATCH v4 1/2] config/arm: add SVE ACLE control flag Thread-Topic: [PATCH v4 1/2] config/arm: add SVE ACLE control flag Thread-Index: AQHYY45Oe/8EvSGH2U6PZgNVNafE9a0iwBSAgAGgyPA= Date: Wed, 18 May 2022 09:18:08 +0000 Message-ID: References: <20220505142744.1423344-1-rbhansali@marvell.com> <20220509101932.2403562-1-rbhansali@marvell.com> <9c1c547ea2c24bcb8c058b70ccbfe026@pantheon.tech> In-Reply-To: <9c1c547ea2c24bcb8c058b70ccbfe026@pantheon.tech> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 7404230d-7ce0-4a1c-4961-08da38af5290 x-ms-traffictypediagnostic: DM6PR18MB3586:EE_ x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO6PR18MB3844.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7404230d-7ce0-4a1c-4961-08da38af5290 X-MS-Exchange-CrossTenant-originalarrivaltime: 18 May 2022 09:18:08.1524 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: r9/UVKjmZpctlvK7Zd3uJtcnMRWmprwQNw8HvGLZf9fY2xRf6MF56jr6JMviJih9NQI7nCbUpHqdILTDSQtw7A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR18MB3586 X-Proofpoint-GUID: BbhHjgE-W4VoRFIGrRKtRZThruf_bX_w X-Proofpoint-ORIG-GUID: BbhHjgE-W4VoRFIGrRKtRZThruf_bX_w X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-18_03,2022-05-17_02,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Juraj Linke=B9 > Sent: Tuesday, May 17, 2022 1:26 PM > To: Rahul Bhansali ; dev@dpdk.org; Ruifeng Wang > ; Jan Viktorin ; Bruce > Richardson > Cc: Jerin Jacob Kollanukkaran > Subject: [EXT] RE: [PATCH v4 1/2] config/arm: add SVE ACLE control flag >=20 > External Email >=20 > ---------------------------------------------------------------------- >=20 >=20 > > -----Original Message----- > > From: Rahul Bhansali > > Sent: Monday, May 9, 2022 12:20 PM > > To: dev@dpdk.org; Ruifeng Wang ; Jan Viktorin > > ; Bruce Richardson > > > > Cc: jerinj@marvell.com; Rahul Bhansali > > Subject: [PATCH v4 1/2] config/arm: add SVE ACLE control flag > > > > This add the control flag for SVE ACLE to enable or disable > > RTE_HAS_SVE_ACLE macro in the build. > > > > Signed-off-by: Rahul Bhansali > > --- > > Changes in v4: > > - Resend patches. With v3, patches were not sent properly in single ser= ies. > > > > Changes in v3: > > - Moved sve_acle condition to be consider for RTE_HAS_SVE_ACLE flag onl= y. > > > > Changes in v2: > > - Renamed the flag to sve_acle from sve > > - Added double-indent. > > > > config/arm/meson.build | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/config/arm/meson.build b/config/arm/meson.build index > > 8aead74086..6f8961eac8 100644 > > --- a/config/arm/meson.build > > +++ b/config/arm/meson.build > > @@ -605,7 +605,7 @@ endif > > > > if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) !=3D '' > > compile_time_cpuflags +=3D ['RTE_CPUFLAG_SVE'] > > - if (cc.check_header('arm_sve.h')) > > + if (cc.check_header('arm_sve.h') and soc_config.get('sve_acle', > > + true)) >=20 > This configuration will be applied only for non-native builds - when we s= pecify > either -Dplatform or do a cross-build (with the target being cn10k). Is t= hat what > we want? I'm not sure how we'd do that for native builds that won't affec= t non- > cn10k builds, as we can do this either at the implementer or part number = level > (both of which cover other SoCs). >=20 For native build, we will need to specify -Dplatform for cn10k so that sve_= acle can be disabled for this only. Currently performance impact of SVE_ACL= E vs Neon is checked on cn10k only, not sure about other platforms, hence n= ot done default SVE ACLE disabled for all platforms. For cn10k, implementor and part number is same as with N2, so not done requ= ired changes at that level.=20 In future, if performance impact is same for other platforms too then we ca= n have this solution based on implementor ID or part number. > > dpdk_conf.set('RTE_HAS_SVE_ACLE', 1) > > endif > > endif > > -- > > 2.25.1 > > >=20