From: Rahul Bhansali <rbhansali@marvell.com>
To: Bruce Richardson <bruce.richardson@intel.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>,
Ruifeng Wang <ruifeng.wang@arm.com>,
Jan Viktorin <viktorin@rehivetech.com>,
Jerin Jacob Kollanukkaran <jerinj@marvell.com>
Subject: RE: [EXT] Re: [PATCH 1/2] config/arm: add SVE control flag
Date: Fri, 6 May 2022 14:16:39 +0000 [thread overview]
Message-ID: <CO6PR18MB384467AD4E273DD7BA6EDD8AB8C59@CO6PR18MB3844.namprd18.prod.outlook.com> (raw)
In-Reply-To: <YnPhlqlRDMJa+RzJ@bricha3-MOBL.ger.corp.intel.com>
> -----Original Message-----
> From: Bruce Richardson <bruce.richardson@intel.com>
> Sent: Thursday, May 5, 2022 8:09 PM
> To: Rahul Bhansali <rbhansali@marvell.com>
> Cc: dev@dpdk.org; Ruifeng Wang <ruifeng.wang@arm.com>; Jan Viktorin
> <viktorin@rehivetech.com>; Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> Subject: [EXT] Re: [PATCH 1/2] config/arm: add SVE control flag
>
> External Email
>
> ----------------------------------------------------------------------
> On Thu, May 05, 2022 at 07:57:43PM +0530, Rahul Bhansali wrote:
> > This add the control flag for SVE to enable or disable
> > RTE_HAS_SVE_ACLE macro in the build.
> >
> > Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
> > ---
> > config/arm/meson.build | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > 8aead74086..dafb342cc6 100644
> > --- a/config/arm/meson.build
> > +++ b/config/arm/meson.build
> > @@ -603,7 +603,8 @@ if (cc.get_define('__ARM_NEON', args: machine_args)
> != '' or
> > compile_time_cpuflags += ['RTE_CPUFLAG_NEON'] endif
> >
> > -if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
> > +if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and
> > + soc_config.get('sve', true))
>
> Please double-indent this so that it does not line up with the following lines of
> the block.
>
Ack, will send v2 with this double-indent change.
> > compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
> > if (cc.check_header('arm_sve.h'))
> > dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
> > --
> > 2.25.1
> >
next prev parent reply other threads:[~2022-05-06 14:16 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-05 14:27 Rahul Bhansali
2022-05-05 14:27 ` [PATCH 2/2] config/arm: disable SVE for cn10k Rahul Bhansali
2022-05-06 2:29 ` fengchengwen
2022-05-06 4:54 ` [EXT] " Rahul Bhansali
2022-05-06 6:36 ` fengchengwen
2022-05-06 7:23 ` Ruifeng Wang
2022-05-06 13:17 ` Rahul Bhansali
2022-05-07 0:52 ` fengchengwen
2022-05-05 14:39 ` [PATCH 1/2] config/arm: add SVE control flag Bruce Richardson
2022-05-06 14:16 ` Rahul Bhansali [this message]
2022-05-06 2:23 ` fengchengwen
2022-05-07 9:39 ` [PATCH v2 1/2] config/arm: add SVE ACLE " Rahul Bhansali
2022-05-07 9:39 ` [PATCH v2 2/2] config/arm: disable SVE ACLE for cn10k Rahul Bhansali
2022-05-09 0:49 ` [PATCH v2 1/2] config/arm: add SVE ACLE control flag fengchengwen
2022-05-09 9:46 ` [PATCH v3 " Rahul Bhansali
2022-05-09 9:46 ` [PATCH v3 2/2] config/arm: disable SVE ACLE for cn10k Rahul Bhansali
2022-05-09 10:19 ` [PATCH v4 1/2] config/arm: add SVE ACLE control flag Rahul Bhansali
2022-05-09 10:19 ` [PATCH v4 2/2] config/arm: disable SVE ACLE for cn10k Rahul Bhansali
2022-05-10 2:57 ` fengchengwen
2022-05-11 1:35 ` Ruifeng Wang
2022-05-11 4:12 ` Honnappa Nagarahalli
2022-05-10 2:57 ` [PATCH v4 1/2] config/arm: add SVE ACLE control flag fengchengwen
2022-05-11 1:35 ` Ruifeng Wang
2022-05-11 4:09 ` Honnappa Nagarahalli
2022-05-17 7:56 ` Juraj Linkeš
2022-05-18 9:18 ` Rahul Bhansali
2022-05-18 14:45 ` Juraj Linkeš
2022-05-19 13:28 ` [PATCH v5 " Rahul Bhansali
2022-05-19 13:28 ` [PATCH v5 2/2] config/arm: disable SVE ACLE for cn10k Rahul Bhansali
2022-06-01 22:38 ` Thomas Monjalon
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