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Wed, 20 Jul 2022 16:52:12 +0000 From: Rahul Bhansali To: Thomas Monjalon , "dev@dpdk.org" CC: Bruce Richardson , "ferruh.yigit@xilinx.com" , "ajit.khaparde@broadcom.com" , "aboyer@pensando.io" , "andrew.rybchenko@oktetlabs.ru" , "beilei.xing@intel.com" , "chas3@att.com" , "chenbo.xia@intel.com" , "ciara.loftus@intel.com" , Devendra Singh Rawat , "ed.czeck@atomicrules.com" , "evgenys@amazon.com" , "grive@u256.net" , "g.singh@nxp.com" , "zhouguoyang@huawei.com" , "haiyue.wang@intel.com" , Harman Kalra , "heinrich.kuhn@corigine.com" , "hemant.agrawal@nxp.com" , "hyonkim@cisco.com" , "igorch@amazon.com" , Igor Russkikh , "jgrajcia@cisco.com" , "jasvinder.singh@intel.com" , "jianwang@trustnetic.com" , "jiawenwu@trustnetic.com" , "jingjing.wu@intel.com" , "johndale@cisco.com" , "john.miller@atomicrules.com" , "linville@tuxdriver.com" , "keith.wiles@intel.com" , Kiran Kumar Kokkilagadda , "oulijun@huawei.com" , Liron Himi , "longli@microsoft.com" , "mw@semihalf.com" , "spinler@cesnet.cz" , "matan@nvidia.com" , "matt.peters@windriver.com" , "maxime.coquelin@redhat.com" , "mk@semihalf.com" , "humin29@huawei.com" , Pradeep Kumar Nalla , Nithin Kumar Dabilpuram , "qiming.yang@intel.com" , "qi.z.zhang@intel.com" , Radha Chintakuntla , "rahul.lakkireddy@chelsio.com" , Rasesh Mody , "rosen.xu@intel.com" , "sachin.saxena@oss.nxp.com" , Satha Koteswara Rao Kottidi , Shahed Shaikh , "shaibran@amazon.com" , "shepard.siegel@atomicrules.com" , "asomalap@amd.com" , "somnath.kotur@broadcom.com" , "sthemmin@microsoft.com" , "steven.webster@windriver.com" , Sunil Kumar Kori , "mtetsuyah@gmail.com" , Veerasenareddy Burru , "viacheslavo@nvidia.com" , "xiao.w.wang@intel.com" , "cloud.wangxiaoyun@huawei.com" , "yisen.zhuang@huawei.com" , "yongwang@vmware.com" , "xuanziyang2@huawei.com" Subject: RE: [EXT] Re: [PATCH] examples/l2fwd: add check of Rx packets count Thread-Topic: [EXT] Re: [PATCH] examples/l2fwd: add check of Rx packets count Thread-Index: AQHYcBfCzbB6aVeY2kKNofhpx15SBK1iYp2AgCVvH+A= Date: Wed, 20 Jul 2022 16:52:11 +0000 Message-ID: References: <20220525091327.4006824-1-rbhansali@marvell.com> <3527350.8uLHfb51uz@thomas> In-Reply-To: <3527350.8uLHfb51uz@thomas> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: dd72550c-7bb8-4569-9825-08da6a703134 x-ms-traffictypediagnostic: SA1PR18MB4677:EE_ x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO6PR18MB3844.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: dd72550c-7bb8-4569-9825-08da6a703134 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Jul 2022 16:52:12.0602 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 1qS4q8c0DuMll6toJhVzqP9SARdA+OKa5uGLg8qUS4xE4dor3P8XnfjcmoamLyTp2V9sn/glMj7KnjJMMEvfZA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR18MB4677 X-Proofpoint-GUID: ZLTRZoViVewkAFboU3MvDxlV8iFSD5n8 X-Proofpoint-ORIG-GUID: ZLTRZoViVewkAFboU3MvDxlV8iFSD5n8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-20_10,2022-07-20_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Ping > -----Original Message----- > From: Thomas Monjalon > Sent: Monday, June 27, 2022 2:42 AM > To: dev@dpdk.org > Cc: Bruce Richardson ; ferruh.yigit@xilinx.co= m; > ajit.khaparde@broadcom.com; aboyer@pensando.io; > andrew.rybchenko@oktetlabs.ru; beilei.xing@intel.com; chas3@att.com; > chenbo.xia@intel.com; ciara.loftus@intel.com; Devendra Singh Rawat > ; ed.czeck@atomicrules.com; > evgenys@amazon.com; grive@u256.net; g.singh@nxp.com; > zhouguoyang@huawei.com; haiyue.wang@intel.com; Harman Kalra > ; heinrich.kuhn@corigine.com; > hemant.agrawal@nxp.com; hyonkim@cisco.com; igorch@amazon.com; Igor > Russkikh ; jgrajcia@cisco.com; > jasvinder.singh@intel.com; jianwang@trustnetic.com; > jiawenwu@trustnetic.com; jingjing.wu@intel.com; johndale@cisco.com; > john.miller@atomicrules.com; linville@tuxdriver.com; keith.wiles@intel.co= m; > Kiran Kumar Kokkilagadda ; oulijun@huawei.com; > Liron Himi ; longli@microsoft.com; mw@semihalf.com; > spinler@cesnet.cz; matan@nvidia.com; matt.peters@windriver.com; > maxime.coquelin@redhat.com; mk@semihalf.com; humin29@huawei.com; > Pradeep Kumar Nalla ; Nithin Kumar Dabilpuram > ; qiming.yang@intel.com; qi.z.zhang@intel.com; > Radha Chintakuntla ; rahul.lakkireddy@chelsio.com; > Rasesh Mody ; rosen.xu@intel.com; > sachin.saxena@oss.nxp.com; Satha Koteswara Rao Kottidi > ; Shahed Shaikh ; > shaibran@amazon.com; shepard.siegel@atomicrules.com; > asomalap@amd.com; somnath.kotur@broadcom.com; > sthemmin@microsoft.com; steven.webster@windriver.com; Sunil Kumar Kori > ; mtetsuyah@gmail.com; Veerasenareddy Burru > ; viacheslavo@nvidia.com; xiao.w.wang@intel.com; > cloud.wangxiaoyun@huawei.com; yisen.zhuang@huawei.com; > yongwang@vmware.com; xuanziyang2@huawei.com; Rahul Bhansali > > Subject: [EXT] Re: [PATCH] examples/l2fwd: add check of Rx packets count >=20 > External Email >=20 > ---------------------------------------------------------------------- > Please could we have some tests on other hardware with this improvement? >=20 >=20 > 25/05/2022 11:13, Rahul Bhansali: > > An additional check is added to avoid extra processing if receive > > packets are 0. > > > > Performance impact: with Marvell OCTEON TX2 platform, observed an > > improvement by ~14%. > > > > Signed-off-by: Rahul Bhansali > > --- > > nb_rx =3D rte_eth_rx_burst(portid, 0, > > pkts_burst, MAX_PKT_BURST); > > > > + if (unlikely(nb_rx =3D=3D 0)) > > + continue; > > + >=20 >=20 >=20