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Sun, 9 Jan 2022 11:18:40 +0000 From: Sunil Kumar Kori To: Sunil Kumar Kori , Nithin Kumar Dabilpuram , Kiran Kumar Kokkilagadda , Satha Koteswara Rao Kottidi CC: "dev@dpdk.org" Subject: RE: [PATCH v1 2/2] net/cnxk: support priority flow control Thread-Topic: [PATCH v1 2/2] net/cnxk: support priority flow control Thread-Index: AQHYBUmv96ZLZfp4hUuyKBlvvAAe8KxaikyA Date: Sun, 9 Jan 2022 11:18:40 +0000 Message-ID: References: <20220109111130.751933-1-skori@marvell.com> <20220109111130.751933-2-skori@marvell.com> In-Reply-To: <20220109111130.751933-2-skori@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 55b28091-fb04-4f25-58da-08d9d361ca54 x-ms-traffictypediagnostic: MW2PR18MB2315:EE_ x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:5236; x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 8x7e67i2OS+wJfl3F4fJt2JboTNQUmVfRZj1jfmDw5eT2hJkq92VJd+Efk6akCPWo5YJj2VwA+Dg06ichV2C//jqpoP1bfxzjVJBDW6OzyFDfqItttzuqdI2SH+8qW28wm15QmaZogyqM9RVbXIpHk9XMQiyTKGrnDHnuAITcKtJKHIJUkFAcrQdQtrcYuXQFWv+37eE8qM+NBPfnQiLdmxQnwQCblOkD3x6Ifj7FbfOC5MLGmbk7yBcgJUcTQqJgwrS84r3YJZjqOSbTeigRTu94QSv6DPCnRYTfHRsPg2O0oyZ48uJnNOTlYSX+3RK2ZubJ9iODwd+q/aduvko72rb48WTPr90bv7tvL/7rGUyklaYHRdmDUFNGgaxvwEavh7tkuiN7nkWR/lNf+bpRdehglcETQGlOSFR8gF656BeNdAwBe7qaqBa5D+0RtqW98z050jdPbVfryhdwnpYCmL6QqBXFwcK3kdYqiJvQ5TICHNw8UQLjyt+6EovjdqZcHRhbHR9VfHlXAiEO41lXAmeLmFECz3dDNNbA9nkO7gZdl46YvVVriDAut86FI/y0VLk2JaHhKi6HDHi1jxx4SnfnIGP48IM7IJj1+15YwGu9hYqNhRFRhydbEG1VpN6y9PSDSsxPhQNlsla/r0L3sfYxNm6Tuo6flSedS9miNFAiy8JObh7R/nQS557I6Zk3bf4o30yJIdSD/thJf3PgeW/4ZfF4s8q8ilI/bMIQr9ejcZaVkdWsPi0vmcySs53ehDBBjO5Xx+2tUSi6TJwfKTKbU81IjkrzkFiAMYrJ85VZmLQqQvv8ib4n1DrpEjS x-forefront-antispam-report: CIP:255.255.255.255; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO6PR18MB3860.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 55b28091-fb04-4f25-58da-08d9d361ca54 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Jan 2022 11:18:40.8043 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jGV/BmZ+FsblX+tj8o4cPjhdZuTFaa3j30TcmBoxvAutiauar94lfvqSMK1ybautGdF+bK+aa387m8+rfUlVFw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR18MB2315 X-Proofpoint-GUID: JKDtajVYY619dxsjxwu4R9ynlNK1FBcM X-Proofpoint-ORIG-GUID: JKDtajVYY619dxsjxwu4R9ynlNK1FBcM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-09_04,2022-01-07_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Following patch sets are dependent on http://patches.dpdk.org/project/dpdk/= patch/20220109105851.734687-1-skori@marvell.com/.=20 Regards Sunil Kumar Kori >-----Original Message----- >From: skori@marvell.com >Sent: Sunday, January 9, 2022 4:42 PM >To: Nithin Kumar Dabilpuram ; Kiran Kumar >Kokkilagadda ; Sunil Kumar Kori >; Satha Koteswara Rao Kottidi > >Cc: dev@dpdk.org >Subject: [PATCH v1 2/2] net/cnxk: support priority flow control > >From: Sunil Kumar Kori > >Patch implements priority flow control support for CNXK platforms. > >Signed-off-by: Sunil Kumar Kori >--- > drivers/net/cnxk/cnxk_ethdev.c | 19 ++++ > drivers/net/cnxk/cnxk_ethdev.h | 16 +++ > drivers/net/cnxk/cnxk_ethdev_ops.c | 177 +++++++++++++++++++++++++++-- > 3 files changed, 203 insertions(+), 9 deletions(-) > >diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev= .c >index 74f625553d..382d88bbf3 100644 >--- a/drivers/net/cnxk/cnxk_ethdev.c >+++ b/drivers/net/cnxk/cnxk_ethdev.c >@@ -1260,6 +1260,8 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) > goto cq_fini; > } > >+ /* Initialize TC to SQ mapping as invalid */ >+ memset(dev->pfc_tc_sq_map, 0xFF, sizeof(dev->pfc_tc_sq_map)); > /* > * Restore queue config when reconfigure followed by > * reconfigure and no queue configure invoked from application case. >@@ -1548,6 +1550,7 @@ struct eth_dev_ops cnxk_eth_dev_ops =3D { > .tx_burst_mode_get =3D cnxk_nix_tx_burst_mode_get, > .flow_ctrl_get =3D cnxk_nix_flow_ctrl_get, > .flow_ctrl_set =3D cnxk_nix_flow_ctrl_set, >+ .priority_flow_ctrl_queue_set =3D >cnxk_nix_priority_flow_ctrl_queue_set, > .dev_set_link_up =3D cnxk_nix_set_link_up, > .dev_set_link_down =3D cnxk_nix_set_link_down, > .get_module_info =3D cnxk_nix_get_module_info, @@ -1721,6 +1724,8 >@@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset) { > struct cnxk_eth_dev *dev =3D cnxk_eth_pmd_priv(eth_dev); > const struct eth_dev_ops *dev_ops =3D eth_dev->dev_ops; >+ struct rte_eth_pfc_queue_conf pfc_conf =3D {0}; >+ struct rte_eth_fc_conf fc_conf =3D {0}; > struct roc_nix *nix =3D &dev->nix; > int rc, i; > >@@ -1736,6 +1741,20 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, >bool reset) > > roc_nix_npc_rx_ena_dis(nix, false); > >+ /* Restore 802.3 Flow control configuration */ >+ fc_conf.mode =3D RTE_ETH_FC_NONE; >+ rc =3D cnxk_nix_flow_ctrl_set(eth_dev, &fc_conf); >+ >+ pfc_conf.mode =3D RTE_ETH_FC_NONE; >+ pfc_conf.rx_pause.tc =3D roc_nix_chan_count_get(nix) - 1; >+ pfc_conf.tx_pause.tc =3D roc_nix_chan_count_get(nix) - 1; >+ rc =3D cnxk_nix_priority_flow_ctrl_queue_set(eth_dev, &pfc_conf); >+ if (rc) >+ plt_err("Failed to reset PFC. error code(%d)", rc); >+ >+ fc_conf.mode =3D RTE_ETH_FC_FULL; >+ rc =3D cnxk_nix_flow_ctrl_set(eth_dev, &fc_conf); >+ > /* Disable and free rte_meter entries */ > nix_meter_fini(dev); > >diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev= .h >index 5bfda3d815..28fb19307a 100644 >--- a/drivers/net/cnxk/cnxk_ethdev.h >+++ b/drivers/net/cnxk/cnxk_ethdev.h >@@ -143,6 +143,16 @@ struct cnxk_fc_cfg { > uint8_t tx_pause; > }; > >+struct cnxk_pfc_cfg { >+ struct cnxk_fc_cfg fc_cfg; >+ uint16_t class_en; >+ uint16_t pause_time; >+ uint8_t rx_tc; >+ uint8_t rx_qid; >+ uint8_t tx_tc; >+ uint8_t tx_qid; >+}; >+ > struct cnxk_eth_qconf { > union { > struct rte_eth_txconf tx; >@@ -366,6 +376,8 @@ struct cnxk_eth_dev { > struct cnxk_eth_qconf *rx_qconf; > > /* Flow control configuration */ >+ uint16_t pfc_tc_sq_map[16]; >+ struct cnxk_pfc_cfg pfc_cfg; > struct cnxk_fc_cfg fc_cfg; > > /* PTP Counters */ >@@ -467,6 +479,8 @@ int cnxk_nix_flow_ctrl_set(struct rte_eth_dev >*eth_dev, > struct rte_eth_fc_conf *fc_conf); int >cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev, > struct rte_eth_fc_conf *fc_conf); >+int cnxk_nix_priority_flow_ctrl_queue_set(struct rte_eth_dev *eth_dev, >+ struct rte_eth_pfc_queue_conf >*pfc_conf); > int cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev); int >cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev); int >cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev, @@ -606,6 +620,8 >@@ int nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t >id, > uint32_t *prev_id, uint32_t *next_id, > struct cnxk_mtr_policy_node *policy, > int *tree_level); >+int nix_priority_flow_ctrl_configure(struct rte_eth_dev *eth_dev, >+ struct cnxk_pfc_cfg *conf); > > /* Inlines */ > static __rte_always_inline uint64_t >diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c >b/drivers/net/cnxk/cnxk_ethdev_ops.c >index ce5f1f7240..27fa2da36d 100644 >--- a/drivers/net/cnxk/cnxk_ethdev_ops.c >+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c >@@ -69,6 +69,8 @@ cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct >rte_eth_dev_info *devinfo) > devinfo->dev_capa =3D >RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | > RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; > devinfo->dev_capa &=3D ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; >+ >+ devinfo->pfc_queue_tc_max =3D roc_nix_chan_count_get(&dev->nix); > return 0; > } > >@@ -230,6 +232,8 @@ nix_fc_cq_config_set(struct cnxk_eth_dev *dev, >uint16_t qid, bool enable) > cq =3D &dev->cqs[qid]; > fc_cfg.type =3D ROC_NIX_FC_CQ_CFG; > fc_cfg.cq_cfg.enable =3D enable; >+ /* Map all CQs to last channel */ >+ fc_cfg.cq_cfg.tc =3D roc_nix_chan_count_get(nix) - 1; > fc_cfg.cq_cfg.rq =3D qid; > fc_cfg.cq_cfg.cq_drop =3D cq->drop_thresh; > >@@ -248,6 +252,8 @@ cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev, > struct rte_eth_dev_data *data =3D eth_dev->data; > struct cnxk_fc_cfg *fc =3D &dev->fc_cfg; > struct roc_nix *nix =3D &dev->nix; >+ struct cnxk_eth_rxq_sp *rxq; >+ struct cnxk_eth_txq_sp *txq; > uint8_t rx_pause, tx_pause; > int rc, i; > >@@ -282,7 +288,12 @@ cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev, > } > > for (i =3D 0; i < data->nb_rx_queues; i++) { >- rc =3D nix_fc_cq_config_set(dev, i, tx_pause); >+ struct roc_nix_fc_cfg fc_cfg; >+ >+ memset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg)); >+ rxq =3D ((struct cnxk_eth_rxq_sp *) >+ data->rx_queues[i]) - 1; >+ rc =3D nix_fc_cq_config_set(dev, rxq->qid, !!tx_pause); > if (rc) > return rc; > } >@@ -290,14 +301,19 @@ cnxk_nix_flow_ctrl_set(struct rte_eth_dev >*eth_dev, > > /* Check if RX pause frame is enabled or not */ > if (fc->rx_pause ^ rx_pause) { >- struct roc_nix_fc_cfg fc_cfg; >- >- memset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg)); >- fc_cfg.type =3D ROC_NIX_FC_TM_CFG; >- fc_cfg.tm_cfg.enable =3D !!rx_pause; >- rc =3D roc_nix_fc_config_set(nix, &fc_cfg); >- if (rc) >- return rc; >+ for (i =3D 0; i < data->nb_tx_queues; i++) { >+ struct roc_nix_fc_cfg fc_cfg; >+ >+ memset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg)); >+ txq =3D ((struct cnxk_eth_txq_sp *) >+ data->tx_queues[i]) - 1; >+ fc_cfg.type =3D ROC_NIX_FC_TM_CFG; >+ fc_cfg.tm_cfg.sq =3D txq->qid; >+ fc_cfg.tm_cfg.enable =3D !!rx_pause; >+ rc =3D roc_nix_fc_config_set(nix, &fc_cfg); >+ if (rc) >+ return rc; >+ } > } > > rc =3D roc_nix_fc_mode_set(nix, mode_map[fc_conf->mode]); @@ - >311,6 +327,29 @@ cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev, > return rc; > } > >+int >+cnxk_nix_priority_flow_ctrl_queue_set(struct rte_eth_dev *eth_dev, >+ struct rte_eth_pfc_queue_conf *pfc_conf) { >+ struct cnxk_pfc_cfg conf =3D {0}; >+ int rc; >+ >+ conf.fc_cfg.mode =3D pfc_conf->mode; >+ >+ conf.pause_time =3D pfc_conf->tx_pause.pause_time; >+ conf.rx_tc =3D pfc_conf->tx_pause.tc; >+ conf.rx_qid =3D pfc_conf->tx_pause.rx_qid; >+ >+ conf.tx_tc =3D pfc_conf->rx_pause.tc; >+ conf.tx_qid =3D pfc_conf->rx_pause.tx_qid; >+ >+ rc =3D nix_priority_flow_ctrl_configure(eth_dev, &conf); >+ if (rc) >+ return rc; >+ >+ return rc; >+} >+ > int > cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev, > const struct rte_flow_ops **ops) @@ -911,3 +950,123 @@ >cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev, > > return 0; > } >+ >+int >+nix_priority_flow_ctrl_configure(struct rte_eth_dev *eth_dev, >+ struct cnxk_pfc_cfg *conf) >+{ >+ enum roc_nix_fc_mode mode_map[] =3D {ROC_NIX_FC_NONE, >ROC_NIX_FC_RX, >+ ROC_NIX_FC_TX, ROC_NIX_FC_FULL}; >+ struct cnxk_eth_dev *dev =3D cnxk_eth_pmd_priv(eth_dev); >+ struct rte_eth_dev_data *data =3D eth_dev->data; >+ struct cnxk_pfc_cfg *pfc =3D &dev->pfc_cfg; >+ struct roc_nix *nix =3D &dev->nix; >+ struct roc_nix_pfc_cfg pfc_cfg; >+ struct roc_nix_fc_cfg fc_cfg; >+ struct cnxk_eth_rxq_sp *rxq; >+ struct cnxk_eth_txq_sp *txq; >+ uint8_t rx_pause, tx_pause; >+ enum rte_eth_fc_mode mode; >+ struct roc_nix_cq *cq; >+ struct roc_nix_sq *sq; >+ int rc; >+ >+ if (roc_nix_is_vf_or_sdp(nix)) { >+ plt_err("Prio flow ctrl config is not allowed on VF and SDP"); >+ return -ENOTSUP; >+ } >+ >+ if (roc_model_is_cn96_ax() && data->dev_started) { >+ /* On Ax, CQ should be in disabled state >+ * while setting flow control configuration. >+ */ >+ plt_info("Stop the port=3D%d for setting flow control", >+ data->port_id); >+ return 0; >+ } >+ >+ if (dev->pfc_tc_sq_map[conf->tx_tc] !=3D 0xFFFF && >+ dev->pfc_tc_sq_map[conf->tx_tc] !=3D conf->tx_qid) { >+ plt_err("Same TC can not be configured on multiple SQs"); >+ return -ENOTSUP; >+ } >+ >+ mode =3D conf->fc_cfg.mode; >+ rx_pause =3D (mode =3D=3D RTE_FC_FULL) || (mode =3D=3D RTE_FC_RX_PAUSE); >+ tx_pause =3D (mode =3D=3D RTE_FC_FULL) || (mode =3D=3D RTE_FC_TX_PAUSE); >+ >+ /* Configure CQs */ >+ memset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg)); >+ rxq =3D ((struct cnxk_eth_rxq_sp *)data->rx_queues[conf->rx_qid]) - 1; >+ cq =3D &dev->cqs[rxq->qid]; >+ fc_cfg.type =3D ROC_NIX_FC_CQ_CFG; >+ fc_cfg.cq_cfg.tc =3D conf->rx_tc; >+ fc_cfg.cq_cfg.enable =3D !!tx_pause; >+ fc_cfg.cq_cfg.rq =3D cq->qid; >+ fc_cfg.cq_cfg.cq_drop =3D cq->drop_thresh; >+ rc =3D roc_nix_fc_config_set(nix, &fc_cfg); >+ if (rc) >+ goto exit; >+ >+ /* Check if RX pause frame is enabled or not */ >+ if (pfc->fc_cfg.rx_pause ^ rx_pause) { >+ if (conf->tx_qid >=3D eth_dev->data->nb_tx_queues) >+ goto exit; >+ >+ if ((roc_nix_tm_tree_type_get(nix) !=3D ROC_NIX_TM_PFC) && >+ eth_dev->data->nb_tx_queues > 1) { >+ /* >+ * Disabled xmit will be enabled when >+ * new topology is available. >+ */ >+ rc =3D roc_nix_tm_hierarchy_disable(nix); >+ if (rc) >+ goto exit; >+ >+ rc =3D roc_nix_tm_prepare_pfc_tree(nix); >+ if (rc) >+ goto exit; >+ >+ rc =3D roc_nix_tm_hierarchy_enable(nix, >ROC_NIX_TM_PFC, >+ true); >+ if (rc) >+ goto exit; >+ } >+ } >+ >+ txq =3D ((struct cnxk_eth_txq_sp *)data->rx_queues[conf->tx_qid]) - 1; >+ sq =3D &dev->sqs[txq->qid]; >+ memset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg)); >+ fc_cfg.type =3D ROC_NIX_FC_TM_CFG; >+ fc_cfg.tm_cfg.sq =3D sq->qid; >+ fc_cfg.tm_cfg.tc =3D conf->tx_tc; >+ fc_cfg.tm_cfg.enable =3D !!rx_pause; >+ rc =3D roc_nix_fc_config_set(nix, &fc_cfg); >+ if (rc) >+ return rc; >+ >+ dev->pfc_tc_sq_map[conf->tx_tc] =3D sq->qid; >+ >+ /* Configure MAC block */ >+ if (tx_pause) >+ pfc->class_en |=3D BIT(conf->rx_tc); >+ else >+ pfc->class_en &=3D ~BIT(conf->rx_tc); >+ >+ if (pfc->class_en) >+ mode =3D RTE_ETH_FC_FULL; >+ >+ memset(&pfc_cfg, 0, sizeof(struct roc_nix_pfc_cfg)); >+ pfc_cfg.mode =3D mode_map[mode]; >+ pfc_cfg.tc =3D conf->rx_tc; >+ rc =3D roc_nix_pfc_mode_set(nix, &pfc_cfg); >+ if (rc) >+ return rc; >+ >+ pfc->fc_cfg.rx_pause =3D rx_pause; >+ pfc->fc_cfg.tx_pause =3D tx_pause; >+ pfc->fc_cfg.mode =3D mode; >+ >+exit: >+ return rc; >+} >-- >2.25.1