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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO6PR18MB4484.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3e76bb08-7ebb-43f4-ab23-08d9dcd19535 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Jan 2022 11:31:35.8452 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: X9UwYrBg2AQz5PAUiXCyGsnR//iaKGi/Odfgpu7yirSvxVsQzrRkLiFdVXZLQTM/x6/Pop3Cs0fwl+sFFkV/aA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR18MB4417 X-Proofpoint-GUID: BbkmcpKfVlYDxCsKM2Zf7llNkgSXuh4q X-Proofpoint-ORIG-GUID: BbkmcpKfVlYDxCsKM2Zf7llNkgSXuh4q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-21_06,2022-01-21_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > From: Nipun Gupta >=20 > This patch supports ordered queue for DPAA2 platform. >=20 > Signed-off-by: Nipun Gupta > --- > drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 255 +++++++++++++++++++- > drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h | 8 +- > drivers/crypto/dpaa2_sec/mc/fsl_dpseci.h | 14 +- > 3 files changed, 263 insertions(+), 14 deletions(-) >=20 > +static uint16_t > +dpaa2_sec_enqueue_burst_ordered(void *qp, struct rte_crypto_op **ops, > + uint16_t nb_ops) > +{ > + /* Function to transmit the frames to given device and VQ*/ > + uint32_t loop; > + int32_t ret; > + struct qbman_fd fd_arr[MAX_TX_RING_SLOTS]; > + uint32_t frames_to_send, num_free_eq_desc, retry_count; > + struct qbman_eq_desc eqdesc[MAX_TX_RING_SLOTS]; > + struct dpaa2_sec_qp *dpaa2_qp =3D (struct dpaa2_sec_qp *)qp; > + struct qbman_swp *swp; > + uint16_t num_tx =3D 0; > + /*todo - need to support multiple buffer pools */ Remove/fix TODO >=20 > @@ -3780,6 +3983,40 @@ dpaa2_sec_eventq_attach(const struct > rte_cryptodev *dev, > cfg.options |=3D DPSECI_QUEUE_OPT_ORDER_PRESERVATION; > cfg.order_preservation_en =3D 1; > } > + > + if (event->sched_type =3D=3D RTE_SCHED_TYPE_ORDERED) { > + struct opr_cfg ocfg; > + > + /* Restoration window size =3D 256 frames */ > + ocfg.oprrws =3D 3; > + /* Restoration window size =3D 512 frames for LX2 */ > + if (dpaa2_svr_family =3D=3D SVR_LX2160A) > + ocfg.oprrws =3D 4; > + /* Auto advance NESN window enabled */ > + ocfg.oa =3D 1; > + /* Late arrival window size disabled */ > + ocfg.olws =3D 0; > + /* ORL resource exhaustaion advance NESN disabled */ > + ocfg.oeane =3D 0; > + /* Loose ordering enabled */ > + ocfg.oloe =3D 1; > + priv->en_loose_ordered =3D 1; > + /* Strict ordering enabled if explicitly set */ > + if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) { > + ocfg.oloe =3D 0; > + priv->en_loose_ordered =3D 0; > + } Can we use devarg to enable strict ordering instead of env variable? Also need to document this.