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Wed, 21 Sep 2022 19:00:08 +0000 From: Akhil Goyal To: Nicolas Chautru , "dev@dpdk.org" , "thomas@monjalon.net" , "hemant.agrawal@nxp.com" CC: "maxime.coquelin@redhat.com" , "trix@redhat.com" , "mdr@ashroe.eu" , "bruce.richardson@intel.com" , "david.marchand@redhat.com" , "stephen@networkplumber.org" , "mingshan.zhang@intel.com" Subject: RE: [EXT] [PATCH v7 4/7] drivers/baseband: update PMDs to expose queue per operation Thread-Topic: [EXT] [PATCH v7 4/7] drivers/baseband: update PMDs to expose queue per operation Thread-Index: AQHYu9Uf9Ju2/8mm0UKOP0DZZueyFa3qYIFA Date: Wed, 21 Sep 2022 19:00:07 +0000 Message-ID: References: <1655491040-183649-6-git-send-email-nicolas.chautru@intel.com> <1661796438-204861-1-git-send-email-nicolas.chautru@intel.com> <1661796438-204861-5-git-send-email-nicolas.chautru@intel.com> In-Reply-To: <1661796438-204861-5-git-send-email-nicolas.chautru@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: CO6PR18MB4484:EE_|SJ0PR18MB4416:EE_ x-ms-office365-filtering-correlation-id: 162346ea-9cd7-47d4-5694-08da9c038076 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO6PR18MB4484.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 162346ea-9cd7-47d4-5694-08da9c038076 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Sep 2022 19:00:08.0264 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 6pwbIfVYFNDGOKqYe1Lkuy0DXRa6/gM2+N8c0XcsIr6L5TXIS3gr4KHiydKPX75qudT7F6Up72OlUnEybffCoA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR18MB4416 X-Proofpoint-ORIG-GUID: 1HGWoHPjI8osAkVlRLImrapQpXoL7C6m X-Proofpoint-GUID: 1HGWoHPjI8osAkVlRLImrapQpXoL7C6m X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-21_09,2022-09-20_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > Add support in existing bbdev PMDs for the explicit number of queues > and priority for each operation type configured on the device. >=20 > Signed-off-by: Nicolas Chautru > Acked-by: Maxime Coquelin > --- > drivers/baseband/acc100/rte_acc100_pmd.c | 29 +++++++++++++---= ------ > drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 8 ++++++ > drivers/baseband/fpga_lte_fec/fpga_lte_fec.c | 8 ++++++ > drivers/baseband/la12xx/bbdev_la12xx.c | 7 ++++++ > drivers/baseband/turbo_sw/bbdev_turbo_software.c | 11 ++++++++ > 5 files changed, 51 insertions(+), 12 deletions(-) >=20 > diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c > b/drivers/baseband/acc100/rte_acc100_pmd.c > index 17ba798..f967e3f 100644 > --- a/drivers/baseband/acc100/rte_acc100_pmd.c > +++ b/drivers/baseband/acc100/rte_acc100_pmd.c > @@ -966,6 +966,7 @@ > struct rte_bbdev_driver_info *dev_info) > { > struct acc100_device *d =3D dev->data->dev_private; > + int i; >=20 > static const struct rte_bbdev_op_cap bbdev_capabilities[] =3D { > { > @@ -1062,19 +1063,23 @@ > fetch_acc100_config(dev); > dev_info->device_status =3D RTE_BBDEV_DEV_NOT_SUPPORTED; >=20 > - /* This isn't ideal because it reports the maximum number of queues but > - * does not provide info on how many can be uplink/downlink or > different > - * priorities > - */ > - dev_info->max_num_queues =3D > - d->acc100_conf.q_dl_5g.num_aqs_per_groups * > - d->acc100_conf.q_dl_5g.num_qgroups + > - d->acc100_conf.q_ul_5g.num_aqs_per_groups * > - d->acc100_conf.q_ul_5g.num_qgroups + > - d->acc100_conf.q_dl_4g.num_aqs_per_groups * > - d->acc100_conf.q_dl_4g.num_qgroups + > - d->acc100_conf.q_ul_4g.num_aqs_per_groups * > + /* Expose number of queues */ > + dev_info->num_queues[RTE_BBDEV_OP_NONE] =3D 0; > + dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] =3D d- > >acc100_conf.q_ul_4g.num_aqs_per_groups * > d->acc100_conf.q_ul_4g.num_qgroups; > + dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] =3D d- > >acc100_conf.q_dl_4g.num_aqs_per_groups * > + d->acc100_conf.q_dl_4g.num_qgroups; > + dev_info->num_queues[RTE_BBDEV_OP_LDPC_DEC] =3D d- > >acc100_conf.q_ul_5g.num_aqs_per_groups * > + d->acc100_conf.q_ul_5g.num_qgroups; > + dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] =3D d- > >acc100_conf.q_dl_5g.num_aqs_per_groups * > + d->acc100_conf.q_dl_5g.num_qgroups; > + dev_info->queue_priority[RTE_BBDEV_OP_TURBO_DEC] =3D d- > >acc100_conf.q_ul_4g.num_qgroups; > + dev_info->queue_priority[RTE_BBDEV_OP_TURBO_ENC] =3D d- > >acc100_conf.q_dl_4g.num_qgroups; > + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC] =3D d- > >acc100_conf.q_ul_5g.num_qgroups; > + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC] =3D d- > >acc100_conf.q_dl_5g.num_qgroups; > + dev_info->max_num_queues =3D 0; > + for (i =3D RTE_BBDEV_OP_TURBO_DEC; i <=3D RTE_BBDEV_OP_LDPC_ENC; > i++) > + dev_info->max_num_queues +=3D dev_info->num_queues[i]; > dev_info->queue_size_lim =3D ACC100_MAX_QUEUE_DEPTH; > dev_info->hardware_accelerated =3D true; > dev_info->max_dl_queue_priority =3D > diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > index 57b12af..b4982af 100644 > --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > @@ -379,6 +379,14 @@ > if (hw_q_id !=3D FPGA_INVALID_HW_QUEUE_ID) > dev_info->max_num_queues++; > } > + /* Expose number of queue per operation type */ > + dev_info->num_queues[RTE_BBDEV_OP_NONE] =3D 0; > + dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] =3D 0; > + dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] =3D 0; > + dev_info->num_queues[RTE_BBDEV_OP_LDPC_DEC] =3D dev_info- > >max_num_queues / 2; > + dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] =3D dev_info- > >max_num_queues / 2; > + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC] =3D 1; > + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC] =3D 1; > } >=20 > /** > diff --git a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c > b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c > index 2a330c4..dc7f479 100644 > --- a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c > +++ b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c > @@ -655,6 +655,14 @@ struct __rte_cache_aligned fpga_queue { > if (hw_q_id !=3D FPGA_INVALID_HW_QUEUE_ID) > dev_info->max_num_queues++; > } > + /* Expose number of queue per operation type */ > + dev_info->num_queues[RTE_BBDEV_OP_NONE] =3D 0; > + dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] =3D dev_info- > >max_num_queues / 2; > + dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] =3D dev_info- > >max_num_queues / 2; > + dev_info->num_queues[RTE_BBDEV_OP_LDPC_DEC] =3D 0; > + dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] =3D 0; > + dev_info->queue_priority[RTE_BBDEV_OP_TURBO_DEC] =3D 1; > + dev_info->queue_priority[RTE_BBDEV_OP_TURBO_ENC] =3D 1; > } >=20 > /** > diff --git a/drivers/baseband/la12xx/bbdev_la12xx.c > b/drivers/baseband/la12xx/bbdev_la12xx.c > index c1f88c6..e99ea9a 100644 > --- a/drivers/baseband/la12xx/bbdev_la12xx.c > +++ b/drivers/baseband/la12xx/bbdev_la12xx.c > @@ -102,6 +102,13 @@ struct bbdev_la12xx_params { > dev_info->min_alignment =3D 64; > dev_info->device_status =3D RTE_BBDEV_DEV_NOT_SUPPORTED; >=20 > + dev_info->num_queues[RTE_BBDEV_OP_NONE] =3D 0; > + dev_info->num_queues[RTE_BBDEV_OP_TURBO_DEC] =3D 0; > + dev_info->num_queues[RTE_BBDEV_OP_TURBO_ENC] =3D 0; > + dev_info->num_queues[RTE_BBDEV_OP_LDPC_DEC] =3D > LA12XX_MAX_QUEUES / 2; > + dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] =3D > LA12XX_MAX_QUEUES / 2; > + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC] =3D 1; > + dev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC] =3D 1; > rte_bbdev_log_debug("got device info from %u", dev->data->dev_id); > } >=20 > diff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c > b/drivers/baseband/turbo_sw/bbdev_turbo_software.c > index dbc5524..647e706 100644 > --- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c > +++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c > @@ -256,6 +256,17 @@ struct turbo_sw_queue { > dev_info->data_endianness =3D RTE_LITTLE_ENDIAN; > dev_info->device_status =3D RTE_BBDEV_DEV_NOT_SUPPORTED; >=20 > + const struct rte_bbdev_op_cap *op_cap =3D bbdev_capabilities; > + int num_op_type =3D 0; Variables should not be defined in middle of the function. Also add a blank line after that. > + for (; op_cap->type !=3D RTE_BBDEV_OP_NONE; ++op_cap) > + num_op_type++; > + op_cap =3D bbdev_capabilities; > + if (num_op_type > 0) { > + int num_queue_per_type =3D dev_info->max_num_queues / > num_op_type; > + for (; op_cap->type !=3D RTE_BBDEV_OP_NONE; ++op_cap) > + dev_info->num_queues[op_cap->type] =3D > num_queue_per_type; > + } > + > rte_bbdev_log_debug("got device info from %u\n", dev->data->dev_id); > } >=20 > -- > 1.8.3.1