[PATCH v2 0/2] crypto/qat: add sm3 and sm4 algorithms

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* [PATCH v2 0/2] crypto/qat: add sm3 and sm4 algorithms
@ 2022-09-30  9:41 Arek Kusztal
  2022-09-30  9:41 ` [PATCH v2 1/2] crypto/qat: add SM4 encryption algorithm Arek Kusztal
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Arek Kusztal @ 2022-09-30  9:41 UTC (permalink / raw)
  To: dev; +Cc: gakhil, kai.ji, Arek Kusztal

ShangMi 4 (SM4) is a block cipher used in the Chinese National Standard for Wireless LAN WAPI and also used with Transport Layer Security.
ShangMi 3 (SM3) is a cryptographic hash function used in the Chinese National Standard.

This patcheset adds both to the Intel QuickAssist Technology PMD.

Depends-on: series-24882 ("cryptodev: add SM3 and SM4 algorithms")

v2:
- Fixed hardcoded number.

Arek Kusztal (2):
  crypto/qat: add SM4 encryption algorithm
  crypto/qat : add SM3 hash algorithm

 doc/guides/cryptodevs/features/qat.ini       |  4 +++
 doc/guides/rel_notes/release_22_11.rst       |  7 ++++++
 drivers/common/qat/qat_adf/icp_qat_hw.h      |  4 ++-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c |  9 +++++++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c |  9 +++++++
 drivers/crypto/qat/qat_sym_session.c         | 37 +++++++++++++++++++++++++---
 6 files changed, 65 insertions(+), 5 deletions(-)

-- 
2.13.6


^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH v2 1/2] crypto/qat: add SM4 encryption algorithm
  2022-09-30  9:41 [PATCH v2 0/2] crypto/qat: add sm3 and sm4 algorithms Arek Kusztal
@ 2022-09-30  9:41 ` Arek Kusztal
  2022-09-30  9:41 ` [PATCH v2 2/2] crypto/qat : add SM3 hash algorithm Arek Kusztal
  2022-09-30 17:44 ` [EXT] [PATCH v2 0/2] crypto/qat: add sm3 and sm4 algorithms Akhil Goyal
  2 siblings, 0 replies; 4+ messages in thread
From: Arek Kusztal @ 2022-09-30  9:41 UTC (permalink / raw)
  To: dev; +Cc: gakhil, kai.ji, Arek Kusztal

- Added ShangMi 4 (SM4) encryption algorithms.
Supported modes: ECB, CBC, CTR.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
 doc/guides/cryptodevs/features/qat.ini       |  3 +++
 doc/guides/rel_notes/release_22_11.rst       |  4 ++++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c |  9 +++++++++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c |  9 +++++++++
 drivers/crypto/qat/qat_sym_session.c         | 12 ++++++++++++
 5 files changed, 37 insertions(+)

diff --git a/doc/guides/cryptodevs/features/qat.ini b/doc/guides/cryptodevs/features/qat.ini
index b9755a757e..edabc030d7 100644
--- a/doc/guides/cryptodevs/features/qat.ini
+++ b/doc/guides/cryptodevs/features/qat.ini
@@ -40,6 +40,9 @@ KASUMI F8      = Y
 AES DOCSIS BPI = Y
 DES DOCSIS BPI = Y
 ZUC EEA3       = Y
+SM4 ECB        = Y
+SM4 CBC        = Y
+SM4 CTR        = Y
 ;
 ; Supported authentication algorithms of the 'qat' crypto driver.
 ;
diff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst
index d6278f1ff0..42aba19af7 100644
--- a/doc/guides/rel_notes/release_22_11.rst
+++ b/doc/guides/rel_notes/release_22_11.rst
@@ -105,6 +105,10 @@ New Features
 
    Added ``RTE_CRYPTO_AUTH_SM3`` to the auth algorithm list in the cryptodev.
 
+* **Updated the Intel QuickAssist Technology (QAT) symmetric crypto PMD.**
+
+   Added SM4 encryption algorithm to the QAT PMD.
+   Supported modes are ECB, CBC and CTR.
 
 Removed Items
 -------------
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
index 2d5f10aeac..d1285cdbd4 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
@@ -131,6 +131,15 @@ static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen3[] = {
 		CAP_RNG(key_size, 32, 32, 0),
 		CAP_RNG(digest_size, 16, 16, 0),
 		CAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 12, 12, 0)),
+	QAT_SYM_CIPHER_CAP(SM4_ECB,
+		CAP_SET(block_size, 16),
+		CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 0, 0, 0)),
+	QAT_SYM_CIPHER_CAP(SM4_CBC,
+		CAP_SET(block_size, 16),
+		CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),
+	QAT_SYM_CIPHER_CAP(SM4_CTR,
+		CAP_SET(block_size, 16),
+		CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),
 	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
index a9457d9278..efbbbda4b6 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
@@ -91,6 +91,15 @@ static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen4[] = {
 		CAP_RNG(key_size, 32, 32, 0),
 		CAP_RNG(digest_size, 16, 16, 0),
 		CAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 12, 12, 0)),
+	QAT_SYM_CIPHER_CAP(SM4_ECB,
+		CAP_SET(block_size, 16),
+		CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 0, 0, 0)),
+	QAT_SYM_CIPHER_CAP(SM4_CBC,
+		CAP_SET(block_size, 16),
+		CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),
+	QAT_SYM_CIPHER_CAP(SM4_CTR,
+		CAP_SET(block_size, 16),
+		CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),
 	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 52b3455cf0..68a38aa69b 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -465,6 +465,18 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev,
 		}
 		session->qat_mode = ICP_QAT_HW_CIPHER_XTS_MODE;
 		break;
+	case RTE_CRYPTO_CIPHER_SM4_ECB:
+		session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_SM4;
+		session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
+		break;
+	case RTE_CRYPTO_CIPHER_SM4_CBC:
+		session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_SM4;
+		session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
+		break;
+	case RTE_CRYPTO_CIPHER_SM4_CTR:
+		session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_SM4;
+		session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
+		break;
 	case RTE_CRYPTO_CIPHER_3DES_ECB:
 	case RTE_CRYPTO_CIPHER_AES_ECB:
 	case RTE_CRYPTO_CIPHER_AES_F8:
-- 
2.13.6


^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH v2 2/2] crypto/qat : add SM3 hash algorithm
  2022-09-30  9:41 [PATCH v2 0/2] crypto/qat: add sm3 and sm4 algorithms Arek Kusztal
  2022-09-30  9:41 ` [PATCH v2 1/2] crypto/qat: add SM4 encryption algorithm Arek Kusztal
@ 2022-09-30  9:41 ` Arek Kusztal
  2022-09-30 17:44 ` [EXT] [PATCH v2 0/2] crypto/qat: add sm3 and sm4 algorithms Akhil Goyal
  2 siblings, 0 replies; 4+ messages in thread
From: Arek Kusztal @ 2022-09-30  9:41 UTC (permalink / raw)
  To: dev; +Cc: gakhil, kai.ji, Arek Kusztal

- Added ShangMi 3 (SM3) hash algorithm.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
 doc/guides/cryptodevs/features/qat.ini  |  1 +
 doc/guides/rel_notes/release_22_11.rst  |  3 +++
 drivers/common/qat/qat_adf/icp_qat_hw.h |  4 +++-
 drivers/crypto/qat/qat_sym_session.c    | 25 +++++++++++++++++++++----
 4 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/doc/guides/cryptodevs/features/qat.ini b/doc/guides/cryptodevs/features/qat.ini
index edabc030d7..4508becc56 100644
--- a/doc/guides/cryptodevs/features/qat.ini
+++ b/doc/guides/cryptodevs/features/qat.ini
@@ -65,6 +65,7 @@ KASUMI F9    = Y
 AES XCBC MAC = Y
 ZUC EIA3     = Y
 AES CMAC (128) = Y
+SM3          = Y
 
 ;
 ; Supported AEAD algorithms of the 'qat' crypto driver.
diff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst
index 42aba19af7..c1b28065a4 100644
--- a/doc/guides/rel_notes/release_22_11.rst
+++ b/doc/guides/rel_notes/release_22_11.rst
@@ -110,6 +110,9 @@ New Features
    Added SM4 encryption algorithm to the QAT PMD.
    Supported modes are ECB, CBC and CTR.
 
+   Added SM3 hash algorithm to the QAT PMD.
+
+
 Removed Items
 -------------
 
diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h
index b1e6a1fa15..e2da701f37 100644
--- a/drivers/common/qat/qat_adf/icp_qat_hw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h
@@ -46,7 +46,7 @@ enum icp_qat_hw_auth_algo {
 	ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12,
 	ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13,
 	ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14,
-	ICP_QAT_HW_AUTH_RESERVED_1 = 15,
+	ICP_QAT_HW_AUTH_ALGO_SM3 = 15,
 	ICP_QAT_HW_AUTH_RESERVED_2 = 16,
 	ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,
 	ICP_QAT_HW_AUTH_RESERVED_3 = 18,
@@ -134,6 +134,7 @@ struct icp_qat_hw_auth_setup {
 #define ICP_QAT_HW_SHA224_STATE1_SZ 32
 #define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
 #define ICP_QAT_HW_SHA256_STATE1_SZ 32
+#define ICP_QAT_HW_SM3_STATE1_SZ 32
 #define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
 #define ICP_QAT_HW_SHA384_STATE1_SZ 64
 #define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
@@ -153,6 +154,7 @@ struct icp_qat_hw_auth_setup {
 #define ICP_QAT_HW_SHA224_STATE2_SZ 32
 #define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
 #define ICP_QAT_HW_SHA256_STATE2_SZ 32
+#define ICP_QAT_HW_SM3_STATE2_SZ 32
 #define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
 #define ICP_QAT_HW_SHA384_STATE2_SZ 64
 #define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 68a38aa69b..bfc9836351 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -102,6 +102,13 @@ static const uint8_t sha512InitialState[] = {
 	0x2b, 0x3e, 0x6c, 0x1f, 0x1f, 0x83, 0xd9, 0xab, 0xfb, 0x41, 0xbd,
 	0x6b, 0x5b, 0xe0, 0xcd, 0x19, 0x13, 0x7e, 0x21, 0x79};
 
+static uint8_t sm3InitialState[] = {
+	0x73, 0x80, 0x16, 0x6f, 0x49, 0x14, 0xb2, 0xb9,
+	0x17, 0x24, 0x42, 0xd7, 0xda, 0x8a, 0x06, 0x00,
+	0xa9, 0x6f, 0x30, 0xbc, 0x16, 0x31, 0x38, 0xaa,
+	0xe3, 0x8d, 0xee, 0x4d, 0xb0, 0xfb, 0x0e, 0x4e
+};
+
 static int
 qat_sym_cd_cipher_set(struct qat_sym_session *cd,
 						const uint8_t *enckey,
@@ -708,6 +715,10 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
 	session->digest_length = auth_xform->digest_length;
 
 	switch (auth_xform->algo) {
+	case RTE_CRYPTO_AUTH_SM3:
+		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SM3;
+		session->auth_mode = ICP_QAT_HW_AUTH_MODE2;
+		break;
 	case RTE_CRYPTO_AUTH_SHA1:
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
 		session->auth_mode = ICP_QAT_HW_AUTH_MODE0;
@@ -1051,6 +1062,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg)
 	case ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC:
 		return QAT_HW_ROUND_UP(ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ,
 						QAT_HW_DEFAULT_ALIGNMENT);
+	case ICP_QAT_HW_AUTH_ALGO_SM3:
+		return QAT_HW_ROUND_UP(ICP_QAT_HW_SM3_STATE1_SZ,
+						QAT_HW_DEFAULT_ALIGNMENT);
 	case ICP_QAT_HW_AUTH_ALGO_NULL:
 		return QAT_HW_ROUND_UP(ICP_QAT_HW_NULL_STATE1_SZ,
 						QAT_HW_DEFAULT_ALIGNMENT);
@@ -2069,11 +2083,14 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
 	}
 
 	cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_auth_setup);
-
-	/*
-	 * cd_cur_ptr now points at the state1 information.
-	 */
 	switch (cdesc->qat_hash_alg) {
+	case ICP_QAT_HW_AUTH_ALGO_SM3:
+		rte_memcpy(cdesc->cd_cur_ptr, sm3InitialState,
+				sizeof(sm3InitialState));
+		state1_size = qat_hash_get_state1_size(
+				cdesc->qat_hash_alg);
+		state2_size = ICP_QAT_HW_SM3_STATE2_SZ;
+		break;
 	case ICP_QAT_HW_AUTH_ALGO_SHA1:
 		if (cdesc->auth_mode == ICP_QAT_HW_AUTH_MODE0) {
 			/* Plain SHA-1 */
-- 
2.13.6


^ permalink raw reply	[flat|nested] 4+ messages in thread

* RE: [EXT] [PATCH v2 0/2] crypto/qat: add sm3 and sm4 algorithms
  2022-09-30  9:41 [PATCH v2 0/2] crypto/qat: add sm3 and sm4 algorithms Arek Kusztal
  2022-09-30  9:41 ` [PATCH v2 1/2] crypto/qat: add SM4 encryption algorithm Arek Kusztal
  2022-09-30  9:41 ` [PATCH v2 2/2] crypto/qat : add SM3 hash algorithm Arek Kusztal
@ 2022-09-30 17:44 ` Akhil Goyal
  2 siblings, 0 replies; 4+ messages in thread
From: Akhil Goyal @ 2022-09-30 17:44 UTC (permalink / raw)
  To: Arek Kusztal, dev; +Cc: kai.ji

> ShangMi 4 (SM4) is a block cipher used in the Chinese National Standard for
> Wireless LAN WAPI and also used with Transport Layer Security.
> ShangMi 3 (SM3) is a cryptographic hash function used in the Chinese National
> Standard.
> 
> This patcheset adds both to the Intel QuickAssist Technology PMD.
> 
> Depends-on: series-24882 ("cryptodev: add SM3 and SM4 algorithms")
> 
> v2:
> - Fixed hardcoded number.
> 
> Arek Kusztal (2):
>   crypto/qat: add SM4 encryption algorithm
>   crypto/qat : add SM3 hash algorithm
> 
>  doc/guides/cryptodevs/features/qat.ini       |  4 +++
>  doc/guides/rel_notes/release_22_11.rst       |  7 ++++++
>  drivers/common/qat/qat_adf/icp_qat_hw.h      |  4 ++-
>  drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c |  9 +++++++
>  drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c |  9 +++++++
>  drivers/crypto/qat/qat_sym_session.c         | 37 +++++++++++++++++++++++++-
> --
applied to dpdk-next-crypto

Thanks.

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2022-09-30 17:44 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2022-09-30  9:41 [PATCH v2 0/2] crypto/qat: add sm3 and sm4 algorithms Arek Kusztal
2022-09-30  9:41 ` [PATCH v2 1/2] crypto/qat: add SM4 encryption algorithm Arek Kusztal
2022-09-30  9:41 ` [PATCH v2 2/2] crypto/qat : add SM3 hash algorithm Arek Kusztal
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