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Thu, 2 Sep 2021 13:46:59 +0000 From: Akhil Goyal To: Hemant Agrawal , "dev@dpdk.org" CC: Gagandeep Singh Thread-Topic: [EXT] [PATCH v2 05/11] crypto/dpaa_sec: add support for AES CMAC integrity check Thread-Index: AQHXmYpU7dHH8Bq0tEeq6WhagUeBWquQzrgQ Date: Thu, 2 Sep 2021 13:46:59 +0000 Message-ID: References: <20210721073920.21893-1-hemant.agrawal@nxp.com> <20210825081837.23830-1-hemant.agrawal@nxp.com> <20210825081837.23830-5-hemant.agrawal@nxp.com> In-Reply-To: <20210825081837.23830-5-hemant.agrawal@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=none action=none header.from=marvell.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 8a27f5e8-a369-4438-56bb-08d96e182328 x-ms-traffictypediagnostic: CO1PR18MB4634: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1417; x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO6PR18MB4484.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8a27f5e8-a369-4438-56bb-08d96e182328 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Sep 2021 13:46:59.6527 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: gixwq1sVABZZX+jUq8XroqE42YsnQCq5tPetwFIaYkO4fpbIF64rIZNxwDDJ5KJvKc+qK9qwhjkeqwFyqRUkGw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR18MB4634 X-Proofpoint-GUID: 5RddtRXjMLfdrrmKQ_UU6SMHcfmsBsw9 X-Proofpoint-ORIG-GUID: 5RddtRXjMLfdrrmKQ_UU6SMHcfmsBsw9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-02_04,2021-09-02_02,2020-04-07_01 Subject: Re: [dpdk-dev] [EXT] [PATCH v2 05/11] crypto/dpaa_sec: add support for AES CMAC integrity check X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > From: Gagandeep Singh >=20 > This patch adds support for AES_CMAC integrity in non-security mode. > This patch modifies the camm flib to handles the AES CMAC > without conflicting the proto ALG operations. i.e. by creating > another ALG operation routine. Description do not match with the patch. Camm flib is not updated in this patch. >=20 > Signed-off-by: Gagandeep Singh > --- > doc/guides/cryptodevs/features/dpaa_sec.ini | 1 + > drivers/crypto/dpaa_sec/dpaa_sec.c | 10 +++++ > drivers/crypto/dpaa_sec/dpaa_sec.h | 43 +++++++++++++++++++++ > 3 files changed, 54 insertions(+) >=20 > diff --git a/doc/guides/cryptodevs/features/dpaa_sec.ini > b/doc/guides/cryptodevs/features/dpaa_sec.ini > index d7bc319373..6a8f77fb1d 100644 > --- a/doc/guides/cryptodevs/features/dpaa_sec.ini > +++ b/doc/guides/cryptodevs/features/dpaa_sec.ini > @@ -48,6 +48,7 @@ SHA512 HMAC =3D Y > SNOW3G UIA2 =3D Y > ZUC EIA3 =3D Y > AES XCBC MAC =3D Y > +AES CMAC (128) =3D Y >=20 > ; > ; Supported AEAD algorithms of the 'dpaa_sec' crypto driver. > diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c > b/drivers/crypto/dpaa_sec/dpaa_sec.c > index dab0ad28c0..7d3f971f3c 100644 > --- a/drivers/crypto/dpaa_sec/dpaa_sec.c > +++ b/drivers/crypto/dpaa_sec/dpaa_sec.c > @@ -525,6 +525,7 @@ dpaa_sec_prep_cdb(dpaa_sec_session *ses) > ses->digest_length); > break; > case RTE_CRYPTO_AUTH_AES_XCBC_MAC: > + case RTE_CRYPTO_AUTH_AES_CMAC: > shared_desc_len =3D cnstr_shdsc_aes_mac( > cdb->sh_desc, > true, swap, SHR_NEVER, > @@ -2177,6 +2178,10 @@ dpaa_sec_auth_init(struct rte_cryptodev *dev > __rte_unused, > session->auth_key.alg =3D OP_ALG_ALGSEL_AES; > session->auth_key.algmode =3D OP_ALG_AAI_XCBC_MAC; > break; > + case RTE_CRYPTO_AUTH_AES_CMAC: > + session->auth_key.alg =3D OP_ALG_ALGSEL_AES; > + session->auth_key.algmode =3D OP_ALG_AAI_CMAC; > + break; > default: > DPAA_SEC_ERR("Crypto: Unsupported Auth specified %u", > xform->auth.algo); > @@ -2262,6 +2267,10 @@ dpaa_sec_chain_init(struct rte_cryptodev *dev > __rte_unused, > session->auth_key.alg =3D OP_ALG_ALGSEL_AES; > session->auth_key.algmode =3D OP_ALG_AAI_XCBC_MAC; > break; > + case RTE_CRYPTO_AUTH_AES_CMAC: > + session->auth_key.alg =3D OP_ALG_ALGSEL_AES; > + session->auth_key.algmode =3D OP_ALG_AAI_CMAC; > + break; > default: > DPAA_SEC_ERR("Crypto: Unsupported Auth specified %u", > auth_xform->algo); > @@ -2697,6 +2706,7 @@ dpaa_sec_ipsec_proto_init(struct > rte_crypto_cipher_xform *cipher_xform, > break; > case RTE_CRYPTO_AUTH_AES_CMAC: > session->auth_key.alg =3D OP_PCL_IPSEC_AES_CMAC_96; > + session->auth_key.algmode =3D OP_ALG_AAI_CMAC; > break; > case RTE_CRYPTO_AUTH_NULL: > session->auth_key.alg =3D OP_PCL_IPSEC_HMAC_NULL; > diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.h > b/drivers/crypto/dpaa_sec/dpaa_sec.h > index 153747c87c..faa740618f 100644 > --- a/drivers/crypto/dpaa_sec/dpaa_sec.h > +++ b/drivers/crypto/dpaa_sec/dpaa_sec.h > @@ -738,6 +738,49 @@ static const struct rte_cryptodev_capabilities > dpaa_sec_capabilities[] =3D { > }, } > }, } > }, > + { /* AES CMAC */ > + .op =3D RTE_CRYPTO_OP_TYPE_SYMMETRIC, > + {.sym =3D { > + .xform_type =3D RTE_CRYPTO_SYM_XFORM_AUTH, > + {.auth =3D { > + .algo =3D RTE_CRYPTO_AUTH_AES_CMAC, > + .block_size =3D 16, > + .key_size =3D { > + .min =3D 1, > + .max =3D 16, > + .increment =3D 1 > + }, > + .digest_size =3D { > + .min =3D 12, > + .max =3D 16, > + .increment =3D 4 > + }, > + .iv_size =3D { 0 } > + }, } > + }, } > + }, > + { /* AES XCBC HMAC */ > + .op =3D RTE_CRYPTO_OP_TYPE_SYMMETRIC, > + {.sym =3D { > + .xform_type =3D RTE_CRYPTO_SYM_XFORM_AUTH, > + {.auth =3D { > + .algo =3D RTE_CRYPTO_AUTH_AES_XCBC_MAC, > + .block_size =3D 16, > + .key_size =3D { > + .min =3D 1, > + .max =3D 16, > + .increment =3D 1 > + }, > + .digest_size =3D { > + .min =3D 12, > + .max =3D 16, > + .increment =3D 4 > + }, > + .aad_size =3D { 0 }, > + .iv_size =3D { 0 } > + }, } > + }, } > + }, > RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() > }; >=20 > -- > 2.17.1