From: Akhil Goyal <gakhil@marvell.com>
To: Anoob Joseph <anoobj@marvell.com>,
Jerin Jacob Kollanukkaran <jerinj@marvell.com>
Cc: Tejasree Kondoj <ktejasree@marvell.com>,
Shijith Thotton <sthotton@marvell.com>,
"dev@dpdk.org" <dev@dpdk.org>
Subject: RE: [PATCH] crypto/cnxk: add CPT hardware flow control checks
Date: Tue, 21 Jun 2022 12:45:36 +0000 [thread overview]
Message-ID: <CO6PR18MB448495E687D01F8D3C166737D8B39@CO6PR18MB4484.namprd18.prod.outlook.com> (raw)
In-Reply-To: <20220620115903.2485-1-anoobj@marvell.com>
> Add hardware supported flow control checks before enqueueing to CPT.
> Since both poll mode and event mode can be used at the same time, add
> hardware flow control checks to make sure s/w doesn't over submit to
> hardware queues. For cn9k, queue depth usage is not high and so FC check
> is omitted for poll mode.
>
> To allow for more accurate updates, flow control hardware setting is
> updated to give an update per 32 packets. In case of crypto adapter,
> multiple cores can enqueue to the same CPT LF at the same time. To
> allow such a case, flow control threshold is updated when the adapter
> is configured.
>
> Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Applied to dpdk-next-crypto
Thanks.
prev parent reply other threads:[~2022-06-21 12:45 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-20 11:59 Anoob Joseph
2022-06-21 12:45 ` Akhil Goyal [this message]
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