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Fri, 14 Oct 2022 06:33:46 +0000 From: Akhil Goyal To: "Chautru, Nicolas" , "Vargas, Hernan" , "dev@dpdk.org" , "trix@redhat.com" , "maxime.coquelin@redhat.com" CC: "Zhang, Qi Z" Subject: RE: [EXT] [PATCH v3 00/30] baseband/acc100: changes for 22.11 Thread-Topic: [EXT] [PATCH v3 00/30] baseband/acc100: changes for 22.11 Thread-Index: AQHY3aNMW3epBF+ww0uwR9eBJEC8Rq4MS4iAgADnZQCAAD74AA== Date: Fri, 14 Oct 2022 06:33:45 +0000 Message-ID: References: <20221012025346.204394-1-hernan.vargas@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: CO6PR18MB4484:EE_|DM4PR18MB4240:EE_ x-ms-office365-filtering-correlation-id: 527c6df5-46d9-41f2-066e-08daadae0bcc x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: r7NsH3hKzX8cD5lT5x+ugjHnxRdIi73O02WrVRR7FilhoDEACCPrCcPE1mEB4JTCLlFk4e9hXAjl5+sGMerv2JRBZDb9dhw/uiP2mYWIvuaArRcB2hhvHd/4a+Y2OcM8ZCi25521AILEYBS8gsgcqSHgLeA+NI2HofIVJ8n/IUL+BNwyDhUvhO2kJR3U4kg/q03yW7RCyhnW3+Sm8JxAfc7wDxoDI/jWx10j7MjrZKNKBTLU0IuN8agc8mu3iOAvfufD9sTDhalI51SmVCJH8GTNO57M48bT2AsnFEoTUinVcT8jQLCeBp5HcX1Wt5iUXgB2IVKXZRvEtP0itZ/7i+4HpVCLO+O3FmyxlkWvhCg381vWUGcOEkhkmgCWE8hzRAuiX3f6/t9YUBeZCgcEETw7eGtCkM3jOe5TVHS2hUJJUEKHg5Wjxub0e3VVWB6lpKLcp9uXokCP+BqOH53N/xPfGdl0WvxWljm5q3VafNdTBdgI0vIpw/P13pwfNZtBKdniwHMjEit9dgiZnF+Ws+EO6YeB8823kdHlYLn2KFEZQtu8PVOJ5729M8SP5PNlUUkZPoDbXAbV8yPAWBBS4cbEZ+NCWtfTNme/Tn2IbQqWz4DrEZ8+oxqwRuh66o9Rr/x8u5BNKfy2MafGo06RIp+WlmqBC0RdLgrJK1oWaBQjjbngI0u7Qyz6N6TVFAXwv7qJ2gQ/qgsAs+o6/Gko0M2iRJ3bwPcwXvintBdQtrWldrx5coIwy0K0YHHD93R1HgEm2dOa4oNTc0NJIYE16w== x-forefront-antispam-report: CIP:255.255.255.255; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO6PR18MB4484.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 527c6df5-46d9-41f2-066e-08daadae0bcc X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Oct 2022 06:33:45.9858 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: GfGod2xp0j1ZVsTZX+7KQUyf3GLa1mDg5l01ikl7Gxxe5tXP03PyGwEEUPPjDrNAfg4x1SaxEAGx8yhL8MSGLA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR18MB4240 X-Proofpoint-GUID: C6SmmVdeKkNOWaZULW88YE2o_uOooBlf X-Proofpoint-ORIG-GUID: C6SmmVdeKkNOWaZULW88YE2o_uOooBlf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_03,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > > > Hernan Vargas (30): > > > baseband/acc100: fix ring availability calculation > > > baseband/acc100: add function to check AQ availability > > > baseband/acc100: memory leak fix > > > baseband/acc100: add LDPC encoder padding function > > > baseband/acc100: check turbo dec/enc input > > > baseband/acc100: check for unlikely operation vals > > > baseband/acc100: enforce additional check on FCW > > > baseband/acc100: allocate ring/queue mem when NULL > > > baseband/acc100: reduce input length for CRC24B > > > baseband/acc100: fix clearing PF IR outside handler > > > baseband/acc100: set device min alignment to 1 > > > baseband/acc100: add protection for NULL HARQ input > > > baseband/acc100: reset pointer after rte_free > > > baseband/acc100: fix debug print for LDPC FCW > > > baseband/acc100: add enqueue status > > > baseband/acc100: add scatter-gather support > > > baseband/acc100: add HARQ index helper function > > > baseband/acc100: enable input validation by default > > > baseband/acc100: added LDPC transport block support > > > baseband/acc100: update validate LDPC enc/dec > > > baseband/acc100: implement configurable queue depth > > > baseband/acc100: add queue stop operation > > > baseband/acc100: update uplink CB input length > > > baseband/acc100: rename ldpc encode function arg > > > baseband/acc100: update log messages > > > baseband/acc100: store FCW from first CB descriptor > > > baseband/acc100: update device info > > > baseband/acc100: add ring companion address > > > baseband/acc100: add workaround for deRM corner cases > > > baseband/acc100: configure PMON control registers > > > > > > drivers/baseband/acc/acc100_pmd.h | 5 + > > > drivers/baseband/acc/acc_common.h | 10 + > > > drivers/baseband/acc/meson.build | 21 + > > > drivers/baseband/acc/rte_acc100_pmd.c | 1197 > > > ++++++++++++++++++++----- > > > 4 files changed, 1010 insertions(+), 223 deletions(-) > > > > > Hi Hernan/Nicolas, > > > > I see some ifdefs being used in the code and there is no documentation = for > > them On when and how to enable/disable them. > > It would be much like a dead code which is not compiled at all, if any = of the > > build target does not enable them. > > > > Is it possible to replace them with runtime devargs instead of compile = time > > ifdefs? >=20 > In term of documentation gap, that is a fair point: > - I believe the build time variable ACC100_EXT_MEM can be valuable for ve= ry > specific troubleshoot (not for production) to shortcut the DDR on the car= d, but > good point to document in the acc100.rst. > - The RTE_BBDEV_OFFLOAD_COST is used across PMDs for a while. That could > also be added to each PMD .rst. > - The #ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE is to skip validation of use= r > API which protect from negative scenario and hence save a few cycles by n= ot > recommended by default. Can be added to acc100.rst. >=20 > In term of runtime devargs usage, can we decorrelate this from the series= ? If we > introduce such dev args and expose them more explicitly we would need mor= e > updated validation in place, are you okay if we defer such change to next= year? > If really this is a big concern for you for 22.11 (this is indeed not ide= al), we could > limit/strip the upstream of the series to the default build configuration= only > (hence no new #ifdef) but still these options can be genuinely valuable t= o users > (until moved to devargs) so I would prefer to keep as is but with updated > documentation in acc100.rst. >=20 > What do you think? I am ok to skip devargs for now. Can be added in next cycle. Please update the documentation as needed for compile time flags.