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Wed, 21 Sep 2022 19:34:28 +0000 From: Akhil Goyal To: Arek Kusztal , "dev@dpdk.org" CC: "kai.ji@intel.com" Subject: RE: [EXT] [PATCH 4/4] crypto/qat : add SM3 hash algorithm Thread-Topic: [EXT] [PATCH 4/4] crypto/qat : add SM3 hash algorithm Thread-Index: AQHYsgl5JCenUMr1y0OX8GI8RwjGT63qfipA Date: Wed, 21 Sep 2022 19:34:27 +0000 Message-ID: References: <20220817060856.78582-1-arkadiuszx.kusztal@intel.com> <20220817060856.78582-5-arkadiuszx.kusztal@intel.com> In-Reply-To: <20220817060856.78582-5-arkadiuszx.kusztal@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: CO6PR18MB4484:EE_|SJ0PR18MB5163:EE_ x-ms-office365-filtering-correlation-id: 1df81fd7-0e5a-4c51-891c-08da9c084c53 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 2FWDrwEPOGEipatryUOop2aVzJ1O6owPjMW2rb5i391ucIknIQOYw34MC8sCu1z+c38YQppBHi9BqcXtOxVaBdD3S6Fv4Febzskzpq8/Dzh9p4Ql/hV149t2KFysdg0/TPzU7pg0SjYja+ffB1MRb/8jwKfQOPOhRWFPfEpxsrUosUZafH/nqhebuin4e2p+4SU5PSD+N4qG5bh3rU/q540QfoO+4T1u40OuByfLdUayWyYvjztxZaL9S7f2sX+1cSBPUaIktn67979aFKiCqAornKkZqyKdd7cDai7za3vRTys5uLGYd4ozUIrbdm4Y3ulJrpQfopmCvcnfbCDEUz3eTnxOjb/vp78apG2tyrB74aP7cu0K9lITBlJ6XBEGXzK88iB9O4YA26KoTYIB7aaEEPk5BRuH8X15SI3nzrat1o5c8kjYuPZTS0FlD4OxBIhDyNE553hjQXrSdJZelV8/wq8wtPOD29ZJOq2V1S1wxjji3VTGtiNkv7rhCPIJZ094MzC1jsId3GKsxSDFaOnFtxoWe5Uhztrpb5XfRKQJwZYj7rC52JBqL0jNwnjDWKLA0Nr/yaqoma6igaQyWaCMUNcG0+ezw7G7yN05ALniFYwPWKI2vUfc9I1+Stxd7oI/J2JaEcoN+ctMrwd/BT13wI3+YGX7Wt37zPAZ0bfDXunZlY0M2j3IJqoTEpAYgQLEUkVmt7JuA+ZfBIljdET++w1i26xUd2dA59c8CaJnbbqPM5w3hiF6t170S9b9Kubh78DkN2YnQe7qTs2EFw== x-forefront-antispam-report: CIP:255.255.255.255; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO6PR18MB4484.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1df81fd7-0e5a-4c51-891c-08da9c084c53 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Sep 2022 19:34:28.0248 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: OuvnhCd0eHMtvzeGoQ40VwOfx9YbEWWuA4xG1TI9UpZkPdUTTlNIkkpaQFGzpZ9CGfEWtQFDhy0k12NOIW4eUw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR18MB5163 X-Proofpoint-GUID: lrwe7ZjdVzPP15AAibQZQP6MAc4s_qTj X-Proofpoint-ORIG-GUID: lrwe7ZjdVzPP15AAibQZQP6MAc4s_qTj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-21_09,2022-09-20_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Arek Kusztal > Sent: Wednesday, August 17, 2022 11:39 AM > To: dev@dpdk.org > Cc: Akhil Goyal ; kai.ji@intel.com; Arek Kusztal > > Subject: [EXT] [PATCH 4/4] crypto/qat : add SM3 hash algorithm >=20 > External Email >=20 > ---------------------------------------------------------------------- > - Added SM3 hash algorithm. >=20 > Signed-off-by: Arek Kusztal > --- > doc/guides/cryptodevs/features/qat.ini | 1 + > doc/guides/rel_notes/release_22_11.rst | 3 +++ > drivers/common/qat/qat_adf/icp_qat_hw.h | 2 +- > drivers/crypto/qat/qat_sym_session.c | 20 +++++++++++++++++++- > 4 files changed, 24 insertions(+), 2 deletions(-) >=20 > diff --git a/doc/guides/cryptodevs/features/qat.ini > b/doc/guides/cryptodevs/features/qat.ini > index edabc030d7..4508becc56 100644 > --- a/doc/guides/cryptodevs/features/qat.ini > +++ b/doc/guides/cryptodevs/features/qat.ini > @@ -65,6 +65,7 @@ KASUMI F9 =3D Y > AES XCBC MAC =3D Y > ZUC EIA3 =3D Y > AES CMAC (128) =3D Y > +SM3 =3D Y >=20 > ; > ; Supported AEAD algorithms of the 'qat' crypto driver. > diff --git a/doc/guides/rel_notes/release_22_11.rst > b/doc/guides/rel_notes/release_22_11.rst > index c6638ded82..5fb79f741c 100644 > --- a/doc/guides/rel_notes/release_22_11.rst > +++ b/doc/guides/rel_notes/release_22_11.rst > @@ -69,6 +69,9 @@ New Features > Added SM4 encryption algorithm to the QAT PMD. > Supported modes are ECB, CBC and CTR. >=20 > + Added SM3 hash algorithm to the QAT PMD. > + > + > Removed Items > ------------- >=20 > diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h > b/drivers/common/qat/qat_adf/icp_qat_hw.h > index b1e6a1fa15..f6875b5242 100644 > --- a/drivers/common/qat/qat_adf/icp_qat_hw.h > +++ b/drivers/common/qat/qat_adf/icp_qat_hw.h > @@ -46,7 +46,7 @@ enum icp_qat_hw_auth_algo { > ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 =3D 12, > ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 =3D 13, > ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 =3D 14, > - ICP_QAT_HW_AUTH_RESERVED_1 =3D 15, > + ICP_QAT_HW_AUTH_ALGO_SM3 =3D 15, > ICP_QAT_HW_AUTH_RESERVED_2 =3D 16, > ICP_QAT_HW_AUTH_ALGO_SHA3_256 =3D 17, > ICP_QAT_HW_AUTH_RESERVED_3 =3D 18, > diff --git a/drivers/crypto/qat/qat_sym_session.c > b/drivers/crypto/qat/qat_sym_session.c > index f4e0faa8e1..6996c3499b 100644 > --- a/drivers/crypto/qat/qat_sym_session.c > +++ b/drivers/crypto/qat/qat_sym_session.c > @@ -687,6 +687,10 @@ qat_sym_session_configure_auth(struct rte_cryptodev > *dev, > session->digest_length =3D auth_xform->digest_length; >=20 > switch (auth_xform->algo) { > + case RTE_CRYPTO_AUTH_SM3: > + session->qat_hash_alg =3D ICP_QAT_HW_AUTH_ALGO_SM3; > + session->auth_mode =3D ICP_QAT_HW_AUTH_MODE2; > + break; > case RTE_CRYPTO_AUTH_SHA1: > session->qat_hash_alg =3D ICP_QAT_HW_AUTH_ALGO_SHA1; > session->auth_mode =3D ICP_QAT_HW_AUTH_MODE0; > @@ -1092,6 +1096,8 @@ static int qat_hash_get_block_size(enum > icp_qat_hw_auth_algo qat_hash_alg) > return ICP_QAT_HW_AES_BLK_SZ; > case ICP_QAT_HW_AUTH_ALGO_MD5: > return MD5_CBLOCK; > + case ICP_QAT_HW_AUTH_ALGO_SM3: > + return 64; Remove hardcode > case ICP_QAT_HW_AUTH_ALGO_DELIMITER: > /* return maximum block size in this case */ > return SHA512_CBLOCK; > @@ -2035,7 +2041,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session > *cdesc, > || cdesc->is_cnt_zero > ) > hash->auth_counter.counter =3D 0; > - else { > + else if (cdesc->auth_mode =3D=3D ICP_QAT_HW_AUTH_MODE1) { > int block_size =3D qat_hash_get_block_size(cdesc->qat_hash_alg); >=20 > if (block_size < 0) > @@ -2048,7 +2054,19 @@ int qat_sym_cd_auth_set(struct qat_sym_session > *cdesc, > /* > * cd_cur_ptr now points at the state1 information. > */ > + uint8_t state1[] =3D { > + 0x73, 0x80, 0x16, 0x6f, 0x49, 0x14, 0xb2, 0xb9, > + 0x17, 0x24, 0x42, 0xd7, 0xda, 0x8a, 0x06, 0x00, > + 0xa9, 0x6f, 0x30, 0xbc, 0x16, 0x31, 0x38, 0xaa, > + 0xe3, 0x8d, 0xee, 0x4d, 0xb0, 0xfb, 0x0e, 0x4e > + }; > switch (cdesc->qat_hash_alg) { > + case ICP_QAT_HW_AUTH_ALGO_SM3: > + rte_memcpy(cdesc->cd_cur_ptr, state1, > + sizeof(state1)); > + state1_size =3D 32; > + state2_size =3D 32; > + break; > case ICP_QAT_HW_AUTH_ALGO_SHA1: > if (cdesc->auth_mode =3D=3D ICP_QAT_HW_AUTH_MODE0) { > /* Plain SHA-1 */ > -- > 2.13.6