* [PATCH v10] sched: enable CMAN at runtime
[not found] <20220708131431.148279-1-marcinx.danilewicz>
@ 2022-07-08 14:22 ` Marcin Danilewicz
2022-07-15 14:51 ` [PATCH v11] " Marcin Danilewicz
0 siblings, 1 reply; 5+ messages in thread
From: Marcin Danilewicz @ 2022-07-08 14:22 UTC (permalink / raw)
To: dev, jasvinder.singh, cristian.dumitrescu; +Cc: megha.ajmera
Added changes to enable CMAN (RED or PIE) at init
from profile configuration file.
By default CMAN code is enable but not in use, when
there is no RED or PIE profile configured.
Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
---
Log: v2 change in rte_sched.h to avoid ABI breakage.
v3 changes from comments
v4 rebase to 22.07-rc1
v5 rebase to main latest
v6 commit message fixed
v7 changes from comments
v8 with changes from comments
v9 changes from comments
tmgr.c
cman_params set to null
qos_sched/cfg_file.c
removed redundant cman_params to NULL assignement
subport_params[].cman_params assigned
only when CMAN enabled
v10 removed ip_pipelin app build error from change
in tmgr.c
---
config/rte_config.h | 3 -
drivers/net/softnic/rte_eth_softnic_tm.c | 12 --
examples/ip_pipeline/tmgr.c | 75 +-----------
examples/qos_sched/cfg_file.c | 49 +-------
examples/qos_sched/cfg_file.h | 5 -
examples/qos_sched/init.c | 76 +-----------
examples/qos_sched/main.h | 2 -
examples/qos_sched/profile.cfg | 135 +--------------------
examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++
examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++
lib/sched/rte_sched.c | 47 +-------
11 files changed, 298 insertions(+), 391 deletions(-)
create mode 100644 examples/qos_sched/profile_pie.cfg
create mode 100644 examples/qos_sched/profile_red.cfg
diff --git a/config/rte_config.h b/config/rte_config.h
index 46549cb062..ae56a86394 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -88,9 +88,6 @@
/* rte_power defines */
#define RTE_MAX_LCORE_FREQS 64
-/* rte_sched defines */
-// RTE_SCHED_CMAN is not set
-
/* rte_graph defines */
#define RTE_GRAPH_BURST_SIZE 256
#define RTE_LIBRTE_GRAPH_STATS 1
diff --git a/drivers/net/softnic/rte_eth_softnic_tm.c b/drivers/net/softnic/rte_eth_softnic_tm.c
index 6a7766ba1c..3e4bed81e9 100644
--- a/drivers/net/softnic/rte_eth_softnic_tm.c
+++ b/drivers/net/softnic/rte_eth_softnic_tm.c
@@ -420,11 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,
return 0;
}
-#ifdef RTE_SCHED_CMAN
-#define WRED_SUPPORTED 1
-#else
#define WRED_SUPPORTED 0
-#endif
#define STATS_MASK_DEFAULT \
(RTE_TM_STATS_N_PKTS | \
@@ -2300,8 +2296,6 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev, uint32_t tc_id)
return NULL;
}
-#ifdef RTE_SCHED_CMAN
-
static void
wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
{
@@ -2325,12 +2319,6 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
}
}
-#else
-
-#define wred_profiles_set(dev, subport_id)
-
-#endif
-
static struct tm_shared_shaper *
tm_tc_shared_shaper_get(struct rte_eth_dev *dev, struct tm_node *tc_node)
{
diff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c
index b138e885cf..2432b56aee 100644
--- a/examples/ip_pipeline/tmgr.c
+++ b/examples/ip_pipeline/tmgr.c
@@ -17,77 +17,6 @@ static uint32_t n_subport_profiles;
static struct rte_sched_pipe_params
pipe_profile[TMGR_PIPE_PROFILE_MAX];
-#ifdef RTE_SCHED_CMAN
-static struct rte_sched_cman_params cman_params = {
- .red_params = {
- /* Traffic Class 0 Colors Green / Yellow / Red */
- [0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 1 - Colors Green / Yellow / Red */
- [1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 2 - Colors Green / Yellow / Red */
- [2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 3 - Colors Green / Yellow / Red */
- [3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 4 - Colors Green / Yellow / Red */
- [4][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [4][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [4][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 5 - Colors Green / Yellow / Red */
- [5][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [5][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [5][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 6 - Colors Green / Yellow / Red */
- [6][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [6][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [6][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 7 - Colors Green / Yellow / Red */
- [7][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [7][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [7][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 8 - Colors Green / Yellow / Red */
- [8][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [8][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [8][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 9 - Colors Green / Yellow / Red */
- [9][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [9][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [9][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 10 - Colors Green / Yellow / Red */
- [10][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [10][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [10][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 11 - Colors Green / Yellow / Red */
- [11][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [11][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [11][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 12 - Colors Green / Yellow / Red */
- [12][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- },
-};
-#endif /* RTE_SCHED_CMAN */
-
static uint32_t n_pipe_profiles;
static const struct rte_sched_subport_params subport_params_default = {
@@ -96,9 +25,7 @@ static const struct rte_sched_subport_params subport_params_default = {
.pipe_profiles = pipe_profile,
.n_pipe_profiles = 0, /* filled at run time */
.n_max_pipe_profiles = RTE_DIM(pipe_profile),
-#ifdef RTE_SCHED_CMAN
- .cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
+ .cman_params = NULL,
};
static struct tmgr_port_list tmgr_port_list;
diff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c
index 450482f07d..deaa28d391 100644
--- a/examples/qos_sched/cfg_file.c
+++ b/examples/qos_sched/cfg_file.c
@@ -23,6 +23,8 @@
uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
uint32_t n_active_queues;
+struct rte_sched_cman_params cman_params;
+
int
cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port_params)
{
@@ -229,40 +231,6 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg,
return 0;
}
-#ifdef RTE_SCHED_CMAN
-void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
- struct rte_sched_cman_params cman_p)
-{
- int j, k;
- subport_p->cman_params->cman_mode = cman_p.cman_mode;
-
- for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
- if (subport_p->cman_params->cman_mode ==
- RTE_SCHED_CMAN_RED) {
- for (k = 0; k < RTE_COLORS; k++) {
- subport_p->cman_params->red_params[j][k].min_th =
- cman_p.red_params[j][k].min_th;
- subport_p->cman_params->red_params[j][k].max_th =
- cman_p.red_params[j][k].max_th;
- subport_p->cman_params->red_params[j][k].maxp_inv =
- cman_p.red_params[j][k].maxp_inv;
- subport_p->cman_params->red_params[j][k].wq_log2 =
- cman_p.red_params[j][k].wq_log2;
- }
- } else {
- subport_p->cman_params->pie_params[j].qdelay_ref =
- cman_p.pie_params[j].qdelay_ref;
- subport_p->cman_params->pie_params[j].dp_update_interval =
- cman_p.pie_params[j].dp_update_interval;
- subport_p->cman_params->pie_params[j].max_burst =
- cman_p.pie_params[j].max_burst;
- subport_p->cman_params->pie_params[j].tailq_th =
- cman_p.pie_params[j].tailq_th;
- }
- }
-}
-#endif
-
int
cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)
{
@@ -276,12 +244,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
memset(active_queues, 0, sizeof(active_queues));
n_active_queues = 0;
-#ifdef RTE_SCHED_CMAN
- struct rte_sched_cman_params cman_params = {
- .cman_mode = RTE_SCHED_CMAN_RED,
- .red_params = { },
- };
-
if (rte_cfgfile_has_section(cfg, "red")) {
cman_params.cman_mode = RTE_SCHED_CMAN_RED;
@@ -387,7 +349,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
-#endif /* RTE_SCHED_CMAN */
for (i = 0; i < MAX_SCHED_SUBPORTS; i++) {
char sec_name[CFG_NAME_LEN];
@@ -465,9 +426,9 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
}
-#ifdef RTE_SCHED_CMAN
- set_subport_cman_params(subport_params+i, cman_params);
-#endif
+ if (cman_params.cman_mode == RTE_SCHED_CMAN_PIE ||
+ cman_params.cman_mode == RTE_SCHED_CMAN_RED)
+ subport_params[i].cman_params = &cman_params;
}
}
diff --git a/examples/qos_sched/cfg_file.h b/examples/qos_sched/cfg_file.h
index 1a9dce9db5..0dc458aa71 100644
--- a/examples/qos_sched/cfg_file.h
+++ b/examples/qos_sched/cfg_file.h
@@ -12,11 +12,6 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);
int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);
-#ifdef RTE_SCHED_CMAN
-void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
- struct rte_sched_cman_params cman_p);
-#endif
-
int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);
int cfg_load_subport_profile(struct rte_cfgfile *cfg,
diff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c
index 8a0fb8a374..e8b819ffb9 100644
--- a/examples/qos_sched/init.c
+++ b/examples/qos_sched/init.c
@@ -201,78 +201,6 @@ static struct rte_sched_subport_profile_params
},
};
-#ifdef RTE_SCHED_CMAN
-struct rte_sched_cman_params cman_params = {
- .cman_mode = RTE_SCHED_CMAN_RED,
- .red_params = {
- /* Traffic Class 0 Colors Green / Yellow / Red */
- [0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 1 - Colors Green / Yellow / Red */
- [1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 2 - Colors Green / Yellow / Red */
- [2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 3 - Colors Green / Yellow / Red */
- [3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 4 - Colors Green / Yellow / Red */
- [4][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [4][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [4][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 5 - Colors Green / Yellow / Red */
- [5][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [5][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [5][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 6 - Colors Green / Yellow / Red */
- [6][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [6][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [6][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 7 - Colors Green / Yellow / Red */
- [7][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [7][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [7][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 8 - Colors Green / Yellow / Red */
- [8][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [8][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [8][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 9 - Colors Green / Yellow / Red */
- [9][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [9][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [9][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 10 - Colors Green / Yellow / Red */
- [10][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [10][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [10][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 11 - Colors Green / Yellow / Red */
- [11][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [11][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [11][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 12 - Colors Green / Yellow / Red */
- [12][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- },
-};
-#endif /* RTE_SCHED_CMAN */
-
struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
{
.n_pipes_per_subport_enabled = 4096,
@@ -281,9 +209,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
.n_pipe_profiles = sizeof(pipe_profiles) /
sizeof(struct rte_sched_pipe_params),
.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,
-#ifdef RTE_SCHED_CMAN
- .cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
+ .cman_params = NULL,
},
};
diff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h
index 915311bac8..76a68f585f 100644
--- a/examples/qos_sched/main.h
+++ b/examples/qos_sched/main.h
@@ -153,9 +153,7 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
extern uint32_t n_active_queues;
extern struct rte_sched_port_params port_params;
-#ifdef RTE_SCHED_CMAN
extern struct rte_sched_cman_params cman_params;
-#endif
extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];
int app_parse_args(int argc, char **argv);
diff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg
index d4b21c0170..c9ec187c93 100644
--- a/examples/qos_sched/profile.cfg
+++ b/examples/qos_sched/profile.cfg
@@ -73,137 +73,4 @@ tc period = 40 ; Milliseconds
tc 12 oversubscription weight = 1
-tc 12 wrr weights = 1 1 1 1
-
-; RED params per traffic class and color (Green / Yellow / Red)
-;[red]
-;tc 0 wred min = 48 40 32
-;tc 0 wred max = 64 64 64
-;tc 0 wred inv prob = 10 10 10
-;tc 0 wred weight = 9 9 9
-
-;tc 1 wred min = 48 40 32
-;tc 1 wred max = 64 64 64
-;tc 1 wred inv prob = 10 10 10
-;tc 1 wred weight = 9 9 9
-
-;tc 2 wred min = 48 40 32
-;tc 2 wred max = 64 64 64
-;tc 2 wred inv prob = 10 10 10
-;tc 2 wred weight = 9 9 9
-
-;tc 3 wred min = 48 40 32
-;tc 3 wred max = 64 64 64
-;tc 3 wred inv prob = 10 10 10
-;tc 3 wred weight = 9 9 9
-
-;tc 4 wred min = 48 40 32
-;tc 4 wred max = 64 64 64
-;tc 4 wred inv prob = 10 10 10
-;tc 4 wred weight = 9 9 9
-
-;tc 5 wred min = 48 40 32
-;tc 5 wred max = 64 64 64
-;tc 5 wred inv prob = 10 10 10
-;tc 5 wred weight = 9 9 9
-
-;tc 6 wred min = 48 40 32
-;tc 6 wred max = 64 64 64
-;tc 6 wred inv prob = 10 10 10
-;tc 6 wred weight = 9 9 9
-
-;tc 7 wred min = 48 40 32
-;tc 7 wred max = 64 64 64
-;tc 7 wred inv prob = 10 10 10
-;tc 7 wred weight = 9 9 9
-
-;tc 8 wred min = 48 40 32
-;tc 8 wred max = 64 64 64
-;tc 8 wred inv prob = 10 10 10
-;tc 8 wred weight = 9 9 9
-
-;tc 9 wred min = 48 40 32
-;tc 9 wred max = 64 64 64
-;tc 9 wred inv prob = 10 10 10
-;tc 9 wred weight = 9 9 9
-
-;tc 10 wred min = 48 40 32
-;tc 10 wred max = 64 64 64
-;tc 10 wred inv prob = 10 10 10
-;tc 10 wred weight = 9 9 9
-
-;tc 11 wred min = 48 40 32
-;tc 11 wred max = 64 64 64
-;tc 11 wred inv prob = 10 10 10
-;tc 11 wred weight = 9 9 9
-
-;tc 12 wred min = 48 40 32
-;tc 12 wred max = 64 64 64
-;tc 12 wred inv prob = 10 10 10
-;tc 12 wred weight = 9 9 9
-
-[pie]
-tc 0 qdelay ref = 15
-tc 0 max burst = 150
-tc 0 update interval = 15
-tc 0 tailq th = 64
-
-tc 1 qdelay ref = 15
-tc 1 max burst = 150
-tc 1 update interval = 15
-tc 1 tailq th = 64
-
-tc 2 qdelay ref = 15
-tc 2 max burst = 150
-tc 2 update interval = 15
-tc 2 tailq th = 64
-
-tc 3 qdelay ref = 15
-tc 3 max burst = 150
-tc 3 update interval = 15
-tc 3 tailq th = 64
-
-tc 4 qdelay ref = 15
-tc 4 max burst = 150
-tc 4 update interval = 15
-tc 4 tailq th = 64
-
-tc 5 qdelay ref = 15
-tc 5 max burst = 150
-tc 5 update interval = 15
-tc 5 tailq th = 64
-
-tc 6 qdelay ref = 15
-tc 6 max burst = 150
-tc 6 update interval = 15
-tc 6 tailq th = 64
-
-tc 7 qdelay ref = 15
-tc 7 max burst = 150
-tc 7 update interval = 15
-tc 7 tailq th = 64
-
-tc 8 qdelay ref = 15
-tc 8 max burst = 150
-tc 8 update interval = 15
-tc 8 tailq th = 64
-
-tc 9 qdelay ref = 15
-tc 9 max burst = 150
-tc 9 update interval = 15
-tc 9 tailq th = 64
-
-tc 10 qdelay ref = 15
-tc 10 max burst = 150
-tc 10 update interval = 15
-tc 10 tailq th = 64
-
-tc 11 qdelay ref = 15
-tc 11 max burst = 150
-tc 11 update interval = 15
-tc 11 tailq th = 64
-
-tc 12 qdelay ref = 15
-tc 12 max burst = 150
-tc 12 update interval = 15
-tc 12 tailq th = 64
+tc 12 wrr weights = 1 1 1 1
\ No newline at end of file
diff --git a/examples/qos_sched/profile_pie.cfg b/examples/qos_sched/profile_pie.cfg
new file mode 100644
index 0000000000..241f748b33
--- /dev/null
+++ b/examples/qos_sched/profile_pie.cfg
@@ -0,0 +1,142 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+[pie]
+tc 0 qdelay ref = 15
+tc 0 max burst = 150
+tc 0 update interval = 15
+tc 0 tailq th = 64
+
+tc 1 qdelay ref = 15
+tc 1 max burst = 150
+tc 1 update interval = 15
+tc 1 tailq th = 64
+
+tc 2 qdelay ref = 15
+tc 2 max burst = 150
+tc 2 update interval = 15
+tc 2 tailq th = 64
+
+tc 3 qdelay ref = 15
+tc 3 max burst = 150
+tc 3 update interval = 15
+tc 3 tailq th = 64
+
+tc 4 qdelay ref = 15
+tc 4 max burst = 150
+tc 4 update interval = 15
+tc 4 tailq th = 64
+
+tc 5 qdelay ref = 15
+tc 5 max burst = 150
+tc 5 update interval = 15
+tc 5 tailq th = 64
+
+tc 6 qdelay ref = 15
+tc 6 max burst = 150
+tc 6 update interval = 15
+tc 6 tailq th = 64
+
+tc 7 qdelay ref = 15
+tc 7 max burst = 150
+tc 7 update interval = 15
+tc 7 tailq th = 64
+
+tc 8 qdelay ref = 15
+tc 8 max burst = 150
+tc 8 update interval = 15
+tc 8 tailq th = 64
+
+tc 9 qdelay ref = 15
+tc 9 max burst = 150
+tc 9 update interval = 15
+tc 9 tailq th = 64
+
+tc 10 qdelay ref = 15
+tc 10 max burst = 150
+tc 10 update interval = 15
+tc 10 tailq th = 64
+
+tc 11 qdelay ref = 15
+tc 11 max burst = 150
+tc 11 update interval = 15
+tc 11 tailq th = 64
+
+tc 12 qdelay ref = 15
+tc 12 max burst = 150
+tc 12 update interval = 15
+tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_red.cfg b/examples/qos_sched/profile_red.cfg
new file mode 100644
index 0000000000..4486d2799e
--- /dev/null
+++ b/examples/qos_sched/profile_red.cfg
@@ -0,0 +1,143 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+; RED params per traffic class and color (Green / Yellow / Red)
+[red]
+tc 0 wred min = 48 40 32
+tc 0 wred max = 64 64 64
+tc 0 wred inv prob = 10 10 10
+tc 0 wred weight = 9 9 9
+
+tc 1 wred min = 48 40 32
+tc 1 wred max = 64 64 64
+tc 1 wred inv prob = 10 10 10
+tc 1 wred weight = 9 9 9
+
+tc 2 wred min = 48 40 32
+tc 2 wred max = 64 64 64
+tc 2 wred inv prob = 10 10 10
+tc 2 wred weight = 9 9 9
+
+tc 3 wred min = 48 40 32
+tc 3 wred max = 64 64 64
+tc 3 wred inv prob = 10 10 10
+tc 3 wred weight = 9 9 9
+
+tc 4 wred min = 48 40 32
+tc 4 wred max = 64 64 64
+tc 4 wred inv prob = 10 10 10
+tc 4 wred weight = 9 9 9
+
+tc 5 wred min = 48 40 32
+tc 5 wred max = 64 64 64
+tc 5 wred inv prob = 10 10 10
+tc 5 wred weight = 9 9 9
+
+tc 6 wred min = 48 40 32
+tc 6 wred max = 64 64 64
+tc 6 wred inv prob = 10 10 10
+tc 6 wred weight = 9 9 9
+
+tc 7 wred min = 48 40 32
+tc 7 wred max = 64 64 64
+tc 7 wred inv prob = 10 10 10
+tc 7 wred weight = 9 9 9
+
+tc 8 wred min = 48 40 32
+tc 8 wred max = 64 64 64
+tc 8 wred inv prob = 10 10 10
+tc 8 wred weight = 9 9 9
+
+tc 9 wred min = 48 40 32
+tc 9 wred max = 64 64 64
+tc 9 wred inv prob = 10 10 10
+tc 9 wred weight = 9 9 9
+
+tc 10 wred min = 48 40 32
+tc 10 wred max = 64 64 64
+tc 10 wred inv prob = 10 10 10
+tc 10 wred weight = 9 9 9
+
+tc 11 wred min = 48 40 32
+tc 11 wred max = 64 64 64
+tc 11 wred inv prob = 10 10 10
+tc 11 wred weight = 9 9 9
+
+tc 12 wred min = 48 40 32
+tc 12 wred max = 64 64 64
+tc 12 wred inv prob = 10 10 10
+tc 12 wred weight = 9 9 9
diff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c
index 599c7e9536..c5fa9e4582 100644
--- a/lib/sched/rte_sched.c
+++ b/lib/sched/rte_sched.c
@@ -81,13 +81,11 @@ struct rte_sched_queue {
struct rte_sched_queue_extra {
struct rte_sched_queue_stats stats;
-#ifdef RTE_SCHED_CMAN
RTE_STD_C11
union {
struct rte_red red;
struct rte_pie pie;
};
-#endif
};
enum grinder_state {
@@ -179,7 +177,6 @@ struct rte_sched_subport {
/* Pipe queues size */
uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
-#ifdef RTE_SCHED_CMAN
bool cman_enabled;
enum rte_sched_cman_mode cman;
@@ -188,7 +185,6 @@ struct rte_sched_subport {
struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];
struct rte_pie_config pie_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
};
-#endif
/* Scheduling loop detection */
uint32_t pipe_loop;
@@ -1084,7 +1080,6 @@ rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports)
rte_free(port);
}
-#ifdef RTE_SCHED_CMAN
static int
rte_sched_red_config(struct rte_sched_port *port,
struct rte_sched_subport *s,
@@ -1166,7 +1161,6 @@ rte_sched_cman_config(struct rte_sched_port *port,
return -EINVAL;
}
-#endif
int
rte_sched_subport_tc_ov_config(struct rte_sched_port *port,
@@ -1285,7 +1279,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
/* TC oversubscription is enabled by default */
s->tc_ov_enabled = 1;
-#ifdef RTE_SCHED_CMAN
if (params->cman_params != NULL) {
s->cman_enabled = true;
status = rte_sched_cman_config(port, s, params, n_subports);
@@ -1297,7 +1290,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
} else {
s->cman_enabled = false;
}
-#endif
/* Scheduling loop detection */
s->pipe_loop = RTE_SCHED_PIPE_INVALID;
@@ -1823,7 +1815,7 @@ rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
uint32_t tc_index = rte_sched_port_pipe_tc(port, qindex);
uint32_t pkt_len = pkt->pkt_len;
@@ -1849,21 +1841,17 @@ static inline void
rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
uint32_t pkt_len = pkt->pkt_len;
qe->stats.n_pkts_dropped += 1;
qe->stats.n_bytes_dropped += pkt_len;
-#ifdef RTE_SCHED_CMAN
if (subport->cman_enabled)
qe->stats.n_pkts_cman_dropped += n_pkts_cman_dropped;
-#endif
}
-#ifdef RTE_SCHED_CMAN
-
static inline int
rte_sched_port_cman_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
@@ -1908,13 +1896,11 @@ static inline void
rte_sched_port_red_set_queue_empty_timestamp(struct rte_sched_port *port,
struct rte_sched_subport *subport, uint32_t qindex)
{
- if (subport->cman_enabled) {
+ if (subport->cman_enabled && subport->cman == RTE_SCHED_CMAN_RED) {
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
- if (subport->cman == RTE_SCHED_CMAN_RED) {
- struct rte_red *red = &qe->red;
+ struct rte_red *red = &qe->red;
- rte_red_mark_queue_empty(red, port->time);
- }
+ rte_red_mark_queue_empty(red, port->time);
}
}
@@ -1933,29 +1919,6 @@ uint32_t qindex, uint32_t pkt_len, uint64_t time) {
}
}
-#else
-
-static inline int rte_sched_port_cman_drop(struct rte_sched_port *port __rte_unused,
- struct rte_sched_subport *subport __rte_unused,
- struct rte_mbuf *pkt __rte_unused,
- uint32_t qindex __rte_unused,
- uint16_t qlen __rte_unused)
-{
- return 0;
-}
-
-#define rte_sched_port_red_set_queue_empty_timestamp(port, subport, qindex)
-
-static inline void
-rte_sched_port_pie_dequeue(struct rte_sched_subport *subport __rte_unused,
- uint32_t qindex __rte_unused,
- uint32_t pkt_len __rte_unused,
- uint64_t time __rte_unused) {
- /* do-nothing when RTE_SCHED_CMAN not defined */
-}
-
-#endif /* RTE_SCHED_CMAN */
-
#ifdef RTE_SCHED_DEBUG
static inline void
--
2.25.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v11] sched: enable CMAN at runtime
2022-07-08 14:22 ` [PATCH v10] sched: enable CMAN at runtime Marcin Danilewicz
@ 2022-07-15 14:51 ` Marcin Danilewicz
2022-07-26 13:49 ` Singh, Jasvinder
0 siblings, 1 reply; 5+ messages in thread
From: Marcin Danilewicz @ 2022-07-15 14:51 UTC (permalink / raw)
To: dev, jasvinder.singh, cristian.dumitrescu; +Cc: megha.ajmera
Added changes to enable CMAN (RED or PIE) at init
from profile configuration file.
By default CMAN code is enable but not in use, when
there is no RED or PIE profile configured.
Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
---
Log: v2 change in rte_sched.h to avoid ABI breakage.
v3 changes from comments
v4 rebase to 22.07-rc1
v5 rebase to main latest
v6 commit message fixed
v7 changes from comments
v8 with changes from comments
v9 changes from comments
tmgr.c
cman_params set to null
qos_sched/cfg_file.c
removed redundant cman_params to NULL assignement
subport_params[].cman_params assigned
only when CMAN enabled
v10 removed ip_pipeline app build error from change
in tmgr.c
v11 added cman_enabled flag instead
of testing cman_params.cman_mode variable
---
config/rte_config.h | 3 -
drivers/net/softnic/rte_eth_softnic_tm.c | 12 --
examples/ip_pipeline/tmgr.c | 75 +-----------
examples/qos_sched/cfg_file.c | 51 ++------
examples/qos_sched/cfg_file.h | 5 -
examples/qos_sched/init.c | 76 +-----------
examples/qos_sched/main.h | 2 -
examples/qos_sched/profile.cfg | 135 +--------------------
examples/qos_sched/profile_pie.cfg | 142 ++++++++++++++++++++++
examples/qos_sched/profile_red.cfg | 143 +++++++++++++++++++++++
lib/sched/rte_sched.c | 47 +-------
11 files changed, 300 insertions(+), 391 deletions(-)
create mode 100644 examples/qos_sched/profile_pie.cfg
create mode 100644 examples/qos_sched/profile_red.cfg
diff --git a/config/rte_config.h b/config/rte_config.h
index 46549cb062..ae56a86394 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -88,9 +88,6 @@
/* rte_power defines */
#define RTE_MAX_LCORE_FREQS 64
-/* rte_sched defines */
-// RTE_SCHED_CMAN is not set
-
/* rte_graph defines */
#define RTE_GRAPH_BURST_SIZE 256
#define RTE_LIBRTE_GRAPH_STATS 1
diff --git a/drivers/net/softnic/rte_eth_softnic_tm.c b/drivers/net/softnic/rte_eth_softnic_tm.c
index 6a7766ba1c..3e4bed81e9 100644
--- a/drivers/net/softnic/rte_eth_softnic_tm.c
+++ b/drivers/net/softnic/rte_eth_softnic_tm.c
@@ -420,11 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,
return 0;
}
-#ifdef RTE_SCHED_CMAN
-#define WRED_SUPPORTED 1
-#else
#define WRED_SUPPORTED 0
-#endif
#define STATS_MASK_DEFAULT \
(RTE_TM_STATS_N_PKTS | \
@@ -2300,8 +2296,6 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev, uint32_t tc_id)
return NULL;
}
-#ifdef RTE_SCHED_CMAN
-
static void
wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
{
@@ -2325,12 +2319,6 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
}
}
-#else
-
-#define wred_profiles_set(dev, subport_id)
-
-#endif
-
static struct tm_shared_shaper *
tm_tc_shared_shaper_get(struct rte_eth_dev *dev, struct tm_node *tc_node)
{
diff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c
index b138e885cf..2432b56aee 100644
--- a/examples/ip_pipeline/tmgr.c
+++ b/examples/ip_pipeline/tmgr.c
@@ -17,77 +17,6 @@ static uint32_t n_subport_profiles;
static struct rte_sched_pipe_params
pipe_profile[TMGR_PIPE_PROFILE_MAX];
-#ifdef RTE_SCHED_CMAN
-static struct rte_sched_cman_params cman_params = {
- .red_params = {
- /* Traffic Class 0 Colors Green / Yellow / Red */
- [0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 1 - Colors Green / Yellow / Red */
- [1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 2 - Colors Green / Yellow / Red */
- [2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 3 - Colors Green / Yellow / Red */
- [3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 4 - Colors Green / Yellow / Red */
- [4][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [4][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [4][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 5 - Colors Green / Yellow / Red */
- [5][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [5][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [5][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 6 - Colors Green / Yellow / Red */
- [6][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [6][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [6][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 7 - Colors Green / Yellow / Red */
- [7][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [7][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [7][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 8 - Colors Green / Yellow / Red */
- [8][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [8][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [8][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 9 - Colors Green / Yellow / Red */
- [9][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [9][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [9][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 10 - Colors Green / Yellow / Red */
- [10][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [10][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [10][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 11 - Colors Green / Yellow / Red */
- [11][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [11][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [11][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 12 - Colors Green / Yellow / Red */
- [12][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- },
-};
-#endif /* RTE_SCHED_CMAN */
-
static uint32_t n_pipe_profiles;
static const struct rte_sched_subport_params subport_params_default = {
@@ -96,9 +25,7 @@ static const struct rte_sched_subport_params subport_params_default = {
.pipe_profiles = pipe_profile,
.n_pipe_profiles = 0, /* filled at run time */
.n_max_pipe_profiles = RTE_DIM(pipe_profile),
-#ifdef RTE_SCHED_CMAN
- .cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
+ .cman_params = NULL,
};
static struct tmgr_port_list tmgr_port_list;
diff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c
index 450482f07d..3d5d75fcf0 100644
--- a/examples/qos_sched/cfg_file.c
+++ b/examples/qos_sched/cfg_file.c
@@ -23,6 +23,8 @@
uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
uint32_t n_active_queues;
+struct rte_sched_cman_params cman_params;
+
int
cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port_params)
{
@@ -229,43 +231,10 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg,
return 0;
}
-#ifdef RTE_SCHED_CMAN
-void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
- struct rte_sched_cman_params cman_p)
-{
- int j, k;
- subport_p->cman_params->cman_mode = cman_p.cman_mode;
-
- for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
- if (subport_p->cman_params->cman_mode ==
- RTE_SCHED_CMAN_RED) {
- for (k = 0; k < RTE_COLORS; k++) {
- subport_p->cman_params->red_params[j][k].min_th =
- cman_p.red_params[j][k].min_th;
- subport_p->cman_params->red_params[j][k].max_th =
- cman_p.red_params[j][k].max_th;
- subport_p->cman_params->red_params[j][k].maxp_inv =
- cman_p.red_params[j][k].maxp_inv;
- subport_p->cman_params->red_params[j][k].wq_log2 =
- cman_p.red_params[j][k].wq_log2;
- }
- } else {
- subport_p->cman_params->pie_params[j].qdelay_ref =
- cman_p.pie_params[j].qdelay_ref;
- subport_p->cman_params->pie_params[j].dp_update_interval =
- cman_p.pie_params[j].dp_update_interval;
- subport_p->cman_params->pie_params[j].max_burst =
- cman_p.pie_params[j].max_burst;
- subport_p->cman_params->pie_params[j].tailq_th =
- cman_p.pie_params[j].tailq_th;
- }
- }
-}
-#endif
-
int
cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)
{
+ bool cman_enabled = false;
const char *entry;
int i, j, k;
@@ -276,14 +245,9 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
memset(active_queues, 0, sizeof(active_queues));
n_active_queues = 0;
-#ifdef RTE_SCHED_CMAN
- struct rte_sched_cman_params cman_params = {
- .cman_mode = RTE_SCHED_CMAN_RED,
- .red_params = { },
- };
-
if (rte_cfgfile_has_section(cfg, "red")) {
cman_params.cman_mode = RTE_SCHED_CMAN_RED;
+ cman_enabled = true;
for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
char str[32];
@@ -353,6 +317,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
if (rte_cfgfile_has_section(cfg, "pie")) {
cman_params.cman_mode = RTE_SCHED_CMAN_PIE;
+ cman_enabled = true;
for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
char str[32];
@@ -387,7 +352,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
-#endif /* RTE_SCHED_CMAN */
for (i = 0; i < MAX_SCHED_SUBPORTS; i++) {
char sec_name[CFG_NAME_LEN];
@@ -465,9 +429,8 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
}
-#ifdef RTE_SCHED_CMAN
- set_subport_cman_params(subport_params+i, cman_params);
-#endif
+ if (cman_enabled)
+ subport_params[i].cman_params = &cman_params;
}
}
diff --git a/examples/qos_sched/cfg_file.h b/examples/qos_sched/cfg_file.h
index 1a9dce9db5..0dc458aa71 100644
--- a/examples/qos_sched/cfg_file.h
+++ b/examples/qos_sched/cfg_file.h
@@ -12,11 +12,6 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);
int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);
-#ifdef RTE_SCHED_CMAN
-void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
- struct rte_sched_cman_params cman_p);
-#endif
-
int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);
int cfg_load_subport_profile(struct rte_cfgfile *cfg,
diff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c
index 8a0fb8a374..e8b819ffb9 100644
--- a/examples/qos_sched/init.c
+++ b/examples/qos_sched/init.c
@@ -201,78 +201,6 @@ static struct rte_sched_subport_profile_params
},
};
-#ifdef RTE_SCHED_CMAN
-struct rte_sched_cman_params cman_params = {
- .cman_mode = RTE_SCHED_CMAN_RED,
- .red_params = {
- /* Traffic Class 0 Colors Green / Yellow / Red */
- [0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 1 - Colors Green / Yellow / Red */
- [1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 2 - Colors Green / Yellow / Red */
- [2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 3 - Colors Green / Yellow / Red */
- [3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 4 - Colors Green / Yellow / Red */
- [4][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [4][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [4][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 5 - Colors Green / Yellow / Red */
- [5][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [5][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [5][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 6 - Colors Green / Yellow / Red */
- [6][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [6][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [6][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 7 - Colors Green / Yellow / Red */
- [7][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [7][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [7][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 8 - Colors Green / Yellow / Red */
- [8][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [8][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [8][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 9 - Colors Green / Yellow / Red */
- [9][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [9][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [9][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 10 - Colors Green / Yellow / Red */
- [10][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [10][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [10][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 11 - Colors Green / Yellow / Red */
- [11][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [11][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [11][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
-
- /* Traffic Class 12 - Colors Green / Yellow / Red */
- [12][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- [12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
- },
-};
-#endif /* RTE_SCHED_CMAN */
-
struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
{
.n_pipes_per_subport_enabled = 4096,
@@ -281,9 +209,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
.n_pipe_profiles = sizeof(pipe_profiles) /
sizeof(struct rte_sched_pipe_params),
.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,
-#ifdef RTE_SCHED_CMAN
- .cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
+ .cman_params = NULL,
},
};
diff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h
index 915311bac8..76a68f585f 100644
--- a/examples/qos_sched/main.h
+++ b/examples/qos_sched/main.h
@@ -153,9 +153,7 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
extern uint32_t n_active_queues;
extern struct rte_sched_port_params port_params;
-#ifdef RTE_SCHED_CMAN
extern struct rte_sched_cman_params cman_params;
-#endif
extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];
int app_parse_args(int argc, char **argv);
diff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg
index d4b21c0170..c9ec187c93 100644
--- a/examples/qos_sched/profile.cfg
+++ b/examples/qos_sched/profile.cfg
@@ -73,137 +73,4 @@ tc period = 40 ; Milliseconds
tc 12 oversubscription weight = 1
-tc 12 wrr weights = 1 1 1 1
-
-; RED params per traffic class and color (Green / Yellow / Red)
-;[red]
-;tc 0 wred min = 48 40 32
-;tc 0 wred max = 64 64 64
-;tc 0 wred inv prob = 10 10 10
-;tc 0 wred weight = 9 9 9
-
-;tc 1 wred min = 48 40 32
-;tc 1 wred max = 64 64 64
-;tc 1 wred inv prob = 10 10 10
-;tc 1 wred weight = 9 9 9
-
-;tc 2 wred min = 48 40 32
-;tc 2 wred max = 64 64 64
-;tc 2 wred inv prob = 10 10 10
-;tc 2 wred weight = 9 9 9
-
-;tc 3 wred min = 48 40 32
-;tc 3 wred max = 64 64 64
-;tc 3 wred inv prob = 10 10 10
-;tc 3 wred weight = 9 9 9
-
-;tc 4 wred min = 48 40 32
-;tc 4 wred max = 64 64 64
-;tc 4 wred inv prob = 10 10 10
-;tc 4 wred weight = 9 9 9
-
-;tc 5 wred min = 48 40 32
-;tc 5 wred max = 64 64 64
-;tc 5 wred inv prob = 10 10 10
-;tc 5 wred weight = 9 9 9
-
-;tc 6 wred min = 48 40 32
-;tc 6 wred max = 64 64 64
-;tc 6 wred inv prob = 10 10 10
-;tc 6 wred weight = 9 9 9
-
-;tc 7 wred min = 48 40 32
-;tc 7 wred max = 64 64 64
-;tc 7 wred inv prob = 10 10 10
-;tc 7 wred weight = 9 9 9
-
-;tc 8 wred min = 48 40 32
-;tc 8 wred max = 64 64 64
-;tc 8 wred inv prob = 10 10 10
-;tc 8 wred weight = 9 9 9
-
-;tc 9 wred min = 48 40 32
-;tc 9 wred max = 64 64 64
-;tc 9 wred inv prob = 10 10 10
-;tc 9 wred weight = 9 9 9
-
-;tc 10 wred min = 48 40 32
-;tc 10 wred max = 64 64 64
-;tc 10 wred inv prob = 10 10 10
-;tc 10 wred weight = 9 9 9
-
-;tc 11 wred min = 48 40 32
-;tc 11 wred max = 64 64 64
-;tc 11 wred inv prob = 10 10 10
-;tc 11 wred weight = 9 9 9
-
-;tc 12 wred min = 48 40 32
-;tc 12 wred max = 64 64 64
-;tc 12 wred inv prob = 10 10 10
-;tc 12 wred weight = 9 9 9
-
-[pie]
-tc 0 qdelay ref = 15
-tc 0 max burst = 150
-tc 0 update interval = 15
-tc 0 tailq th = 64
-
-tc 1 qdelay ref = 15
-tc 1 max burst = 150
-tc 1 update interval = 15
-tc 1 tailq th = 64
-
-tc 2 qdelay ref = 15
-tc 2 max burst = 150
-tc 2 update interval = 15
-tc 2 tailq th = 64
-
-tc 3 qdelay ref = 15
-tc 3 max burst = 150
-tc 3 update interval = 15
-tc 3 tailq th = 64
-
-tc 4 qdelay ref = 15
-tc 4 max burst = 150
-tc 4 update interval = 15
-tc 4 tailq th = 64
-
-tc 5 qdelay ref = 15
-tc 5 max burst = 150
-tc 5 update interval = 15
-tc 5 tailq th = 64
-
-tc 6 qdelay ref = 15
-tc 6 max burst = 150
-tc 6 update interval = 15
-tc 6 tailq th = 64
-
-tc 7 qdelay ref = 15
-tc 7 max burst = 150
-tc 7 update interval = 15
-tc 7 tailq th = 64
-
-tc 8 qdelay ref = 15
-tc 8 max burst = 150
-tc 8 update interval = 15
-tc 8 tailq th = 64
-
-tc 9 qdelay ref = 15
-tc 9 max burst = 150
-tc 9 update interval = 15
-tc 9 tailq th = 64
-
-tc 10 qdelay ref = 15
-tc 10 max burst = 150
-tc 10 update interval = 15
-tc 10 tailq th = 64
-
-tc 11 qdelay ref = 15
-tc 11 max burst = 150
-tc 11 update interval = 15
-tc 11 tailq th = 64
-
-tc 12 qdelay ref = 15
-tc 12 max burst = 150
-tc 12 update interval = 15
-tc 12 tailq th = 64
+tc 12 wrr weights = 1 1 1 1
\ No newline at end of file
diff --git a/examples/qos_sched/profile_pie.cfg b/examples/qos_sched/profile_pie.cfg
new file mode 100644
index 0000000000..241f748b33
--- /dev/null
+++ b/examples/qos_sched/profile_pie.cfg
@@ -0,0 +1,142 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+[pie]
+tc 0 qdelay ref = 15
+tc 0 max burst = 150
+tc 0 update interval = 15
+tc 0 tailq th = 64
+
+tc 1 qdelay ref = 15
+tc 1 max burst = 150
+tc 1 update interval = 15
+tc 1 tailq th = 64
+
+tc 2 qdelay ref = 15
+tc 2 max burst = 150
+tc 2 update interval = 15
+tc 2 tailq th = 64
+
+tc 3 qdelay ref = 15
+tc 3 max burst = 150
+tc 3 update interval = 15
+tc 3 tailq th = 64
+
+tc 4 qdelay ref = 15
+tc 4 max burst = 150
+tc 4 update interval = 15
+tc 4 tailq th = 64
+
+tc 5 qdelay ref = 15
+tc 5 max burst = 150
+tc 5 update interval = 15
+tc 5 tailq th = 64
+
+tc 6 qdelay ref = 15
+tc 6 max burst = 150
+tc 6 update interval = 15
+tc 6 tailq th = 64
+
+tc 7 qdelay ref = 15
+tc 7 max burst = 150
+tc 7 update interval = 15
+tc 7 tailq th = 64
+
+tc 8 qdelay ref = 15
+tc 8 max burst = 150
+tc 8 update interval = 15
+tc 8 tailq th = 64
+
+tc 9 qdelay ref = 15
+tc 9 max burst = 150
+tc 9 update interval = 15
+tc 9 tailq th = 64
+
+tc 10 qdelay ref = 15
+tc 10 max burst = 150
+tc 10 update interval = 15
+tc 10 tailq th = 64
+
+tc 11 qdelay ref = 15
+tc 11 max burst = 150
+tc 11 update interval = 15
+tc 11 tailq th = 64
+
+tc 12 qdelay ref = 15
+tc 12 max burst = 150
+tc 12 update interval = 15
+tc 12 tailq th = 64
diff --git a/examples/qos_sched/profile_red.cfg b/examples/qos_sched/profile_red.cfg
new file mode 100644
index 0000000000..4486d2799e
--- /dev/null
+++ b/examples/qos_sched/profile_red.cfg
@@ -0,0 +1,143 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+; RED params per traffic class and color (Green / Yellow / Red)
+[red]
+tc 0 wred min = 48 40 32
+tc 0 wred max = 64 64 64
+tc 0 wred inv prob = 10 10 10
+tc 0 wred weight = 9 9 9
+
+tc 1 wred min = 48 40 32
+tc 1 wred max = 64 64 64
+tc 1 wred inv prob = 10 10 10
+tc 1 wred weight = 9 9 9
+
+tc 2 wred min = 48 40 32
+tc 2 wred max = 64 64 64
+tc 2 wred inv prob = 10 10 10
+tc 2 wred weight = 9 9 9
+
+tc 3 wred min = 48 40 32
+tc 3 wred max = 64 64 64
+tc 3 wred inv prob = 10 10 10
+tc 3 wred weight = 9 9 9
+
+tc 4 wred min = 48 40 32
+tc 4 wred max = 64 64 64
+tc 4 wred inv prob = 10 10 10
+tc 4 wred weight = 9 9 9
+
+tc 5 wred min = 48 40 32
+tc 5 wred max = 64 64 64
+tc 5 wred inv prob = 10 10 10
+tc 5 wred weight = 9 9 9
+
+tc 6 wred min = 48 40 32
+tc 6 wred max = 64 64 64
+tc 6 wred inv prob = 10 10 10
+tc 6 wred weight = 9 9 9
+
+tc 7 wred min = 48 40 32
+tc 7 wred max = 64 64 64
+tc 7 wred inv prob = 10 10 10
+tc 7 wred weight = 9 9 9
+
+tc 8 wred min = 48 40 32
+tc 8 wred max = 64 64 64
+tc 8 wred inv prob = 10 10 10
+tc 8 wred weight = 9 9 9
+
+tc 9 wred min = 48 40 32
+tc 9 wred max = 64 64 64
+tc 9 wred inv prob = 10 10 10
+tc 9 wred weight = 9 9 9
+
+tc 10 wred min = 48 40 32
+tc 10 wred max = 64 64 64
+tc 10 wred inv prob = 10 10 10
+tc 10 wred weight = 9 9 9
+
+tc 11 wred min = 48 40 32
+tc 11 wred max = 64 64 64
+tc 11 wred inv prob = 10 10 10
+tc 11 wred weight = 9 9 9
+
+tc 12 wred min = 48 40 32
+tc 12 wred max = 64 64 64
+tc 12 wred inv prob = 10 10 10
+tc 12 wred weight = 9 9 9
diff --git a/lib/sched/rte_sched.c b/lib/sched/rte_sched.c
index 599c7e9536..c5fa9e4582 100644
--- a/lib/sched/rte_sched.c
+++ b/lib/sched/rte_sched.c
@@ -81,13 +81,11 @@ struct rte_sched_queue {
struct rte_sched_queue_extra {
struct rte_sched_queue_stats stats;
-#ifdef RTE_SCHED_CMAN
RTE_STD_C11
union {
struct rte_red red;
struct rte_pie pie;
};
-#endif
};
enum grinder_state {
@@ -179,7 +177,6 @@ struct rte_sched_subport {
/* Pipe queues size */
uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
-#ifdef RTE_SCHED_CMAN
bool cman_enabled;
enum rte_sched_cman_mode cman;
@@ -188,7 +185,6 @@ struct rte_sched_subport {
struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];
struct rte_pie_config pie_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
};
-#endif
/* Scheduling loop detection */
uint32_t pipe_loop;
@@ -1084,7 +1080,6 @@ rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports)
rte_free(port);
}
-#ifdef RTE_SCHED_CMAN
static int
rte_sched_red_config(struct rte_sched_port *port,
struct rte_sched_subport *s,
@@ -1166,7 +1161,6 @@ rte_sched_cman_config(struct rte_sched_port *port,
return -EINVAL;
}
-#endif
int
rte_sched_subport_tc_ov_config(struct rte_sched_port *port,
@@ -1285,7 +1279,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
/* TC oversubscription is enabled by default */
s->tc_ov_enabled = 1;
-#ifdef RTE_SCHED_CMAN
if (params->cman_params != NULL) {
s->cman_enabled = true;
status = rte_sched_cman_config(port, s, params, n_subports);
@@ -1297,7 +1290,6 @@ rte_sched_subport_config(struct rte_sched_port *port,
} else {
s->cman_enabled = false;
}
-#endif
/* Scheduling loop detection */
s->pipe_loop = RTE_SCHED_PIPE_INVALID;
@@ -1823,7 +1815,7 @@ rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
uint32_t tc_index = rte_sched_port_pipe_tc(port, qindex);
uint32_t pkt_len = pkt->pkt_len;
@@ -1849,21 +1841,17 @@ static inline void
rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport *subport,
uint32_t qindex,
struct rte_mbuf *pkt,
- __rte_unused uint32_t n_pkts_cman_dropped)
+ uint32_t n_pkts_cman_dropped)
{
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
uint32_t pkt_len = pkt->pkt_len;
qe->stats.n_pkts_dropped += 1;
qe->stats.n_bytes_dropped += pkt_len;
-#ifdef RTE_SCHED_CMAN
if (subport->cman_enabled)
qe->stats.n_pkts_cman_dropped += n_pkts_cman_dropped;
-#endif
}
-#ifdef RTE_SCHED_CMAN
-
static inline int
rte_sched_port_cman_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
@@ -1908,13 +1896,11 @@ static inline void
rte_sched_port_red_set_queue_empty_timestamp(struct rte_sched_port *port,
struct rte_sched_subport *subport, uint32_t qindex)
{
- if (subport->cman_enabled) {
+ if (subport->cman_enabled && subport->cman == RTE_SCHED_CMAN_RED) {
struct rte_sched_queue_extra *qe = subport->queue_extra + qindex;
- if (subport->cman == RTE_SCHED_CMAN_RED) {
- struct rte_red *red = &qe->red;
+ struct rte_red *red = &qe->red;
- rte_red_mark_queue_empty(red, port->time);
- }
+ rte_red_mark_queue_empty(red, port->time);
}
}
@@ -1933,29 +1919,6 @@ uint32_t qindex, uint32_t pkt_len, uint64_t time) {
}
}
-#else
-
-static inline int rte_sched_port_cman_drop(struct rte_sched_port *port __rte_unused,
- struct rte_sched_subport *subport __rte_unused,
- struct rte_mbuf *pkt __rte_unused,
- uint32_t qindex __rte_unused,
- uint16_t qlen __rte_unused)
-{
- return 0;
-}
-
-#define rte_sched_port_red_set_queue_empty_timestamp(port, subport, qindex)
-
-static inline void
-rte_sched_port_pie_dequeue(struct rte_sched_subport *subport __rte_unused,
- uint32_t qindex __rte_unused,
- uint32_t pkt_len __rte_unused,
- uint64_t time __rte_unused) {
- /* do-nothing when RTE_SCHED_CMAN not defined */
-}
-
-#endif /* RTE_SCHED_CMAN */
-
#ifdef RTE_SCHED_DEBUG
static inline void
--
2.25.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH v11] sched: enable CMAN at runtime
2022-07-15 14:51 ` [PATCH v11] " Marcin Danilewicz
@ 2022-07-26 13:49 ` Singh, Jasvinder
2022-07-27 11:58 ` Danilewicz, MarcinX
2022-08-25 14:09 ` Thomas Monjalon
0 siblings, 2 replies; 5+ messages in thread
From: Singh, Jasvinder @ 2022-07-26 13:49 UTC (permalink / raw)
To: Danilewicz, MarcinX, dev, Dumitrescu, Cristian; +Cc: Ajmera, Megha
> -----Original Message-----
> From: Danilewicz, MarcinX <marcinx.danilewicz@intel.com>
> Sent: Friday, July 15, 2022 3:51 PM
> To: dev@dpdk.org; Singh, Jasvinder <jasvinder.singh@intel.com>;
> Dumitrescu, Cristian <cristian.dumitrescu@intel.com>
> Cc: Ajmera, Megha <megha.ajmera@intel.com>
> Subject: [PATCH v11] sched: enable CMAN at runtime
>
> Added changes to enable CMAN (RED or PIE) at init from profile configuration
> file.
>
> By default CMAN code is enable but not in use, when there is no RED or PIE
> profile configured.
>
> Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
> ---
> Log: v2 change in rte_sched.h to avoid ABI breakage.
> v3 changes from comments
> v4 rebase to 22.07-rc1
> v5 rebase to main latest
> v6 commit message fixed
> v7 changes from comments
> v8 with changes from comments
> v9 changes from comments
> tmgr.c
> cman_params set to null
> qos_sched/cfg_file.c
> removed redundant cman_params to NULL assignement
> subport_params[].cman_params assigned
> only when CMAN enabled
> v10 removed ip_pipeline app build error from change
> in tmgr.c
> v11 added cman_enabled flag instead
> of testing cman_params.cman_mode variable
> ---
Acked-by: Jasvinder Singh <jasvinder.singh@intel.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH v11] sched: enable CMAN at runtime
2022-07-26 13:49 ` Singh, Jasvinder
@ 2022-07-27 11:58 ` Danilewicz, MarcinX
2022-08-25 14:09 ` Thomas Monjalon
1 sibling, 0 replies; 5+ messages in thread
From: Danilewicz, MarcinX @ 2022-07-27 11:58 UTC (permalink / raw)
To: Thomas Monjalon, dev
Cc: Ajmera, Megha, Singh, Jasvinder, Dumitrescu, Cristian
Hi Thomas,
Could you merge this change with the latest DPDK?
Thanks!
Kind Regards,
/Marcin
> -----Original Message-----
> From: Singh, Jasvinder <jasvinder.singh@intel.com>
> Sent: Tuesday, July 26, 2022 3:49 PM
> To: Danilewicz, MarcinX <marcinx.danilewicz@intel.com>; dev@dpdk.org;
> Dumitrescu, Cristian <cristian.dumitrescu@intel.com>
> Cc: Ajmera, Megha <megha.ajmera@intel.com>
> Subject: RE: [PATCH v11] sched: enable CMAN at runtime
>
>
>
> > -----Original Message-----
> > From: Danilewicz, MarcinX <marcinx.danilewicz@intel.com>
> > Sent: Friday, July 15, 2022 3:51 PM
> > To: dev@dpdk.org; Singh, Jasvinder <jasvinder.singh@intel.com>;
> > Dumitrescu, Cristian <cristian.dumitrescu@intel.com>
> > Cc: Ajmera, Megha <megha.ajmera@intel.com>
> > Subject: [PATCH v11] sched: enable CMAN at runtime
> >
> > Added changes to enable CMAN (RED or PIE) at init from profile
> > configuration file.
> >
> > By default CMAN code is enable but not in use, when there is no RED or
> > PIE profile configured.
> >
> > Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
> > ---
> > Log: v2 change in rte_sched.h to avoid ABI breakage.
> > v3 changes from comments
> > v4 rebase to 22.07-rc1
> > v5 rebase to main latest
> > v6 commit message fixed
> > v7 changes from comments
> > v8 with changes from comments
> > v9 changes from comments
> > tmgr.c
> > cman_params set to null
> > qos_sched/cfg_file.c
> > removed redundant cman_params to NULL assignement
> > subport_params[].cman_params assigned
> > only when CMAN enabled
> > v10 removed ip_pipeline app build error from change
> > in tmgr.c
> > v11 added cman_enabled flag instead
> > of testing cman_params.cman_mode variable
> > ---
>
> Acked-by: Jasvinder Singh <jasvinder.singh@intel.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v11] sched: enable CMAN at runtime
2022-07-26 13:49 ` Singh, Jasvinder
2022-07-27 11:58 ` Danilewicz, MarcinX
@ 2022-08-25 14:09 ` Thomas Monjalon
1 sibling, 0 replies; 5+ messages in thread
From: Thomas Monjalon @ 2022-08-25 14:09 UTC (permalink / raw)
To: Danilewicz, MarcinX
Cc: dev, Dumitrescu, Cristian, Ajmera, Megha, Singh, Jasvinder
> > Added changes to enable CMAN (RED or PIE) at init from profile configuration
> > file.
> >
> > By default CMAN code is enable but not in use, when there is no RED or PIE
> > profile configured.
> >
> > Signed-off-by: Marcin Danilewicz <marcinx.danilewicz@intel.com>
>
> Acked-by: Jasvinder Singh <jasvinder.singh@intel.com>
Applied, thanks.
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-08-25 14:09 UTC | newest]
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2022-07-08 14:22 ` [PATCH v10] sched: enable CMAN at runtime Marcin Danilewicz
2022-07-15 14:51 ` [PATCH v11] " Marcin Danilewicz
2022-07-26 13:49 ` Singh, Jasvinder
2022-07-27 11:58 ` Danilewicz, MarcinX
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