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b=Q+wyCDmz1HmSgde5DS0ICXZKt8IUigI30usWt+VfVsFXR+GbVUJlQEyWf2g0NzUuX 1Gr80Dn7STvrfuP/TDCHBVWOyTMpC1f56X6FaSpDecLHxf8aH6OCcc3OUob3Ag+3j2 EC+/HwugjAsLx91dnMgZTwtZCWWrYdqN1ovaLDBdB0oQEozbJLb4dT3S1usZqABgHR ArmhiDqSTqpE0qF7vwcfAMVRwJ5J0IIB1Sz+5w3L22229LtJQpfO+ic1Zks0hZamlG NnbDlzjgF4vnww0EZALAIsrFk2lcstzHsIQLFpUz+SEGLV1xq8m66q1PThcJfh/y5U c8AioejLKdIpg== Subject: Re: [dpdk-dev] [PATCH v3 2/6] ethdev: add new attributes to hairpin config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Archived-At: List-Archive: Hi Thomas, PSB > -----Original Message----- > From: Thomas Monjalon > Sent: Tuesday, October 13, 2020 5:37 AM > To: Bing Zhao > Cc: Ori Kam ; ferruh.yigit@intel.com; > arybchenko@solarflare.com; mdr@ashroe.eu; nhorman@tuxdriver.com; > bernard.iremonger@intel.com; beilei.xing@intel.com; > wenzhuo.lu@intel.com; dev@dpdk.org > Subject: Re: [dpdk-dev] [PATCH v3 2/6] ethdev: add new attributes to > hairpin config >=20 > External email: Use caution opening links or attachments >=20 >=20 > 08/10/2020 14:05, Bing Zhao: > > struct rte_eth_hairpin_conf { > > - uint16_t peer_count; /**< The number of peers. */ > > + uint32_t peer_count:16; /**< The number of peers. */ >=20 > Why not keeping uint16_t? The inside structure has a multiple of 4B, and the peer_count now only take= s about 2B. AFAIK, usually, the structure will have an aligned length/offse= t and there will be some padding between the 2B + (2B pad) + 4B * 32 or 2B = + (2B +2B) * 32 + 2B, depending on the compiler. I changed to bit fields of a u32 due to the two facts: 1. Using the 2B and keep the whole structure aligned. No waste except the r= eserved bits. 2. Only u32 with bit fields is standard. >=20 > > + uint32_t tx_explicit:1; /**< Explicit TX flow rule mode. */ > > + uint32_t manual_bind:1; /**< Manually bind hairpin queues. > */ >=20 > Please describe more the expectations of these bits: > What is changed at ethdev or PMD level? In ethdev level, there is almost no change. This attribute will be passed t= o PMD directly through the function pointer. In PMD level, these bits should be checked and better to be saved. And the = attribute fields should be checked for per queue pair and all the queues, a= nd each queue pair should have the same attributes configured to make the b= ehavior aligned. But it depends on the PMD itself to decide if all the queu= e pairs between a port pair should have the same attributes, or even all th= e queues from / to same port of all hairpin port pairs. If manual_bind is not set, then the PMD will try to bind the queues and ena= ble hairpin during device start stage and there is no need to call the bind= / unbind API. If tx_explicit is set, the application should insert the RX flow rules and = TX flow rules seperataly and connect the RX/TX logic connection together. > What the application is supposed to do? The application should specify the new two attributes during the queue setu= p. And also, it could leave it unset (0 by default) to keep the behavior co= mpatible with the previous release. If manual_bind is set, then it is the application's responsibility to call = the bind / unbind API to enable / disable the hairpin between specific port= s. If tx_explicit is set, as described above, the application should maintain = the flows logic to make hairpin work as expected, e.g., they can choose met= adata (not the only method), in the RX flow, the metadata is set and in the= TX flow, it is used for matching. Then even if the headers are changed wit= h NAT action or encap, the hairpin function could work as expected. > Why choosing one mode or the other? If the application wants to have the full control of hairpin flows, it coul= d chose the explicit TX flow mode. If two or more ports involved into the hairpin, it is suggested to use the = manual bind. Please note, the actual supported attributes denpend on the PMD and HW. >=20 Thanks