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mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none Received: from CY4PR1201MB0072.namprd12.prod.outlook.com (2603:10b6:910:1b::19) by CY4PR12MB1528.namprd12.prod.outlook.com (2603:10b6:910:6::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3433.34; Wed, 7 Oct 2020 11:32:31 +0000 Received: from CY4PR1201MB0072.namprd12.prod.outlook.com ([fe80::f1b2:c80a:e623:e613]) by CY4PR1201MB0072.namprd12.prod.outlook.com ([fe80::f1b2:c80a:e623:e613%11]) with mapi id 15.20.3433.045; Wed, 7 Oct 2020 11:32:31 +0000 From: Bing Zhao To: Ori Kam , NBU-Contact-Thomas Monjalon , "ferruh.yigit@intel.com" , "arybchenko@solarflare.com" , "mdr@ashroe.eu" , "nhorman@tuxdriver.com" , "bernard.iremonger@intel.com" , "beilei.xing@intel.com" , "wenzhuo.lu@intel.com" CC: "dev@dpdk.org" Thread-Topic: [PATCH 2/4] ethdev: add new attributes to hairpin config Thread-Index: AQHWmi/Tyvf4Y8dvlEmN/za2QCkFr6mMA+cQ Date: Wed, 7 Oct 2020 11:32:31 +0000 Message-ID: References: <1600012140-70151-1-git-send-email-bingz@nvidia.com> <1601511962-21532-1-git-send-email-bingz@nvidia.com> <1601511962-21532-3-git-send-email-bingz@nvidia.com> In-Reply-To: Accept-Language: en-US, zh-CN Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: nvidia.com; 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b=bGVK/+4CMvz9mc28sMAEw4HcGatd+dx3Sbh2Cq+BRKihPleMTfBf0RcwV/dq8Zq/2 ChEBwCv3fFjPTQrfOQ2ZdGsdc6Zo8j5+yeTKicKuGORYCnt5g9MYLqqjbvzdW2k4Ne ataSJDNutSw/yzlCwojUPXzXKLO8waSuPSg3J+2Aj3DOlIV2aDfybiD854Ou2OV9rR 3iWTkNc6BljLesat1umSuSk/026MMaNkifIGZns6mtP4q6IOORUiv/3KIsBSNExqPQ NBgUWDmqC6qOwry25zpsiHFIBu7EtXlUEdGEVVOhIHmy50puOJAZbd4K+0tnNScJY5 RlEYMIzf3mg4A== Subject: Re: [dpdk-dev] [PATCH 2/4] ethdev: add new attributes to hairpin config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Ori, > -----Original Message----- > From: Ori Kam > Sent: Sunday, October 4, 2020 5:22 PM > To: Bing Zhao ; NBU-Contact-Thomas Monjalon > ; ferruh.yigit@intel.com; > arybchenko@solarflare.com; mdr@ashroe.eu; nhorman@tuxdriver.com; > bernard.iremonger@intel.com; beilei.xing@intel.com; > wenzhuo.lu@intel.com > Cc: dev@dpdk.org > Subject: RE: [PATCH 2/4] ethdev: add new attributes to hairpin > config >=20 > Hi Bing, >=20 > PSB, > Best, > Ori >=20 > > -----Original Message----- > > From: Bing Zhao > > Sent: Thursday, October 1, 2020 3:26 AM > > Subject: [PATCH 2/4] ethdev: add new attributes to hairpin config > > > > To support two ports hairpin mode and keep the backward > compatibility > > for the application, two new attribute members of hairpin queue > config > > structure are added. > > > > `tx_explicit` means if the application itself will insert the TX > part > > flow rules. If not set, PMD will insert the rules implicitly. > > `manual_bind` means if the hairpin TX queue and peer RX queue will > be > > bound automatically during device start stage. > > > > Different TX and RX queue pairs could have different values, but > it is > > highly recommend that all paired queues between one egress and its > > peer ingress ports have the same values, in order not to bring any > > chaos to the system. The actual support of these attribute > parameters > > will be checked and decided by the PMD driver. > > > > In a single port hairpin, if both are zero without any setting, > the > > behavior will remain the same as before. It means no bind API > needs to > > be called and no TX flow rules need to be inserted manually by the > > application. > > > > Signed-off-by: Bing Zhao > > --- > > lib/librte_ethdev/rte_ethdev.h | 18 ++++++++++++++++++ > > 1 file changed, 18 insertions(+) > > > > diff --git a/lib/librte_ethdev/rte_ethdev.h > > b/lib/librte_ethdev/rte_ethdev.h index c3fb684..0cabff0 100644 > > --- a/lib/librte_ethdev/rte_ethdev.h > > +++ b/lib/librte_ethdev/rte_ethdev.h > > @@ -1027,6 +1027,21 @@ struct rte_eth_hairpin_cap { > > > > #define RTE_ETH_MAX_HAIRPIN_PEERS 32 > > > > +/* > > + * Hairpin queue attribute parameters. > > + * Each TX queue and peer RX queue should have the same value. > > + * Default value 0 is for backward-compatibility, the same > behaviors > > +should > > + * remain if the value is not set (0). > > + */ > > +/**< Hairpin queues will be bound automatically */ > > +#define RTE_ETH_HAIRPIN_BIND_AUTO (0) > > +/**< Hairpin queues will be bound manually with bind API */ > > +#define RTE_ETH_HAIRPIN_BIND_MANUAL (1) > > +/**< Hairpin TX part flow rule will be inserted implicitly by PMD > */ > > +#define RTE_ETH_HAIRPIN_TXRULE_IMPLICIT (0) > > +/**< Hairpin TX part flow rule will be inserted explicitly by APP > */ > > +#define RTE_ETH_HAIRPIN_TXRULE_EXPLICIT (1) > > + >=20 > Why do you need those defines if you are using bit fields? I will remove this and add the description of the modes in the document. >=20 > > /** > > * @warning > > * @b EXPERIMENTAL: this API may change, or be removed, without > prior > > notice @@ -1046,6 +1061,9 @@ struct rte_eth_hairpin_peer { > > */ > > struct rte_eth_hairpin_conf { > > uint16_t peer_count; /**< The number of peers. */ > > + uint32_t reserved : 30; /**< Reserved bits. */ > > + uint32_t tx_explicit : 1; /**< Explicit TX flow rule mode. */ > > + uint32_t manual_bind : 1; /**< Manually bind hairpin queues. > */ >=20 > Why not place the new bits at the end? By using uint16_t bit fields, there will be some warnings by the compiler a= nd it is not standard. I prefer to change the "uint16_t peer_count" into "uint32_t peer_count:16" = to use the gap before the next structure. Or yes, I can move it to the end of this current structure. > Also why do you place the reserved first? Thanks, I will move it to the end of the u32 like other structure definitio= ns. >=20 > > struct rte_eth_hairpin_peer > peers[RTE_ETH_MAX_HAIRPIN_PEERS]; }; > > > > -- > > 2.5.5 Thanks