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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 38529c4f-37d8-4352-593c-08d7b1fb7737 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Feb 2020 09:43:08.8699 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: efrjS81668OnHWB2al2HqUWLdVIdaZ4tNPJS+H5ewSDe+duB+bVrqOrLJYrUfNcUbqosM91ohz66ukzEV/bvB+d6wCoeJUkKdaQzEkstpc0= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1801MB1880 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-15_02:2020-02-14, 2020-02-15 signatures=0 Subject: Re: [dpdk-dev] [PATCH] event/octeontx2: remove WFE from dualslot dequeue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Gavin, >Hi Pavan, > >> -----Original Message----- >> From: pbhagavatula@marvell.com >> Sent: Friday, February 14, 2020 2:45 PM >> To: jerinj@marvell.com; Pavan Nikhilesh > >> Cc: Gavin Hu ; dev@dpdk.org >> Subject: [dpdk-dev] [PATCH] event/octeontx2: remove WFE from >dualslot >> dequeue >> >> From: Pavan Nikhilesh >> >> Each workslot is always bound to a specific lcore there is no multi-core >> contention to cause cache trashing as a result it is safe to remove the >> WFE. Also, in dual workslot dequeue work will mostlikely be available >on >> the pair workslot making WFE impractical. > >Does SSO still signal EVENTI to exit from WFE? Then the core ignore it? All transactions on SSO bus take the core out of WFE. >Can this be disabled as WFE is removed? This can't be disabled. > >> >> Signed-off-by: Pavan Nikhilesh >> --- >> >> Also, this in-turn reduces the branch misses >> >> Before: >> 0 >> >arm_spe_0/ts_enable=3D1,pct_enable=3D1,pa_enable=3D1,branch_filter=3D1,jit >ter=3D1, >> min_latency=3D0/ >> 0 dummy:u >> 0 llc-miss >> 0 tlb-miss >> 853 branch-miss >> 0 remote-access >> 0 l1d-miss >> >> After: >> 0 >> >arm_spe_0/ts_enable=3D1,pct_enable=3D1,pa_enable=3D1,branch_filter=3D1,jit >ter=3D1, >> min_latency=3D0/ >> 0 dummy:u >> 0 llc-miss >> 0 tlb-miss >> 250 branch-miss >> 0 remote-access >> 0 l1d-miss >> >> WFE Data: >> >> 0x4C40 - WFI_WFE_WAIT_CYCLES - Number of cycles waiting at a WFI >or >> WFE instruction. >> >> - WFE Cycles before the patch for Dual workslot >> #perf stat -C 20 -e r4C40 sleep 1 >> Performance counter stats for 'CPU(s) 20': >> >> 264 r4C40 >> 1.002494168 seconds time elapsed >> >> - WFE Cycles for single workslot >> #perf stat -C 20 -e r4C40 sleep 1 >> Performance counter stats for 'CPU(s) 20': >> >> 908,778,351 r4C40 >> 1.002598253 seconds time elapsed >> >> drivers/event/octeontx2/otx2_worker_dual.h | 6 +----- >> 1 file changed, 1 insertion(+), 5 deletions(-) >> >> diff --git a/drivers/event/octeontx2/otx2_worker_dual.h >> b/drivers/event/octeontx2/otx2_worker_dual.h >> index 5134e3d52..c88420eb4 100644 >> --- a/drivers/event/octeontx2/otx2_worker_dual.h >> +++ b/drivers/event/octeontx2/otx2_worker_dual.h >> @@ -29,11 +29,7 @@ otx2_ssogws_dual_get_work(struct >> otx2_ssogws_state *ws, >> rte_prefetch_non_temporal(lookup_mem); >> #ifdef RTE_ARCH_ARM64 >> asm volatile( >> - " ldr %[tag], [%[tag_loc]] \n" >> - " ldr %[wqp], [%[wqp_loc]] \n" >> - " tbz %[tag], 63, done%=3D \n" >> - " sevl \n" >> - "rty%=3D: wfe \n" >> + "rty%=3D: \n" >> " ldr %[tag], [%[tag_loc]] \n" >> " ldr %[wqp], [%[wqp_loc]] \n" >> " tbnz %[tag], 63, rty%=3D \n" >> -- >> 2.17.1