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Fri, 11 Nov 2022 03:34:50 +0000 Received: from CY8PR11MB7136.namprd11.prod.outlook.com ([fe80::bb7a:1ce0:962e:cfe]) by CY8PR11MB7136.namprd11.prod.outlook.com ([fe80::bb7a:1ce0:962e:cfe%8]) with mapi id 15.20.5813.013; Fri, 11 Nov 2022 03:34:50 +0000 From: "Ye, MingjinX" To: "thomas@monjalon.net" , "Zhang, Qi Z" , "Yang, Qiming" CC: "dev@dpdk.org" , "stable@dpdk.org" , "Zhou, YidingX" , "Richardson, Bruce" , Konstantin Ananyev , "Lu, Wenzhuo" , "Junyu Jiang" , "Rong, Leyi" , "Ajit Khaparde" , Jerin Jacob , "Xu, Rosen" , Hemant Agrawal , "Wisam Jaddo" Subject: RE: [PATCH v5 1/2] net/ice: fix vlan offload Thread-Topic: [PATCH v5 1/2] net/ice: fix vlan offload Thread-Index: AQHY8zTDeblszuaVwEOwKquXpbtApK45Ebfw Date: Fri, 11 Nov 2022 03:34:49 +0000 Message-ID: References: <20221026171007.654038-1-mingjinx.ye@intel.com> <20221108132804.714764-1-mingjinx.ye@intel.com> In-Reply-To: <20221108132804.714764-1-mingjinx.ye@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; 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charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CY8PR11MB7136.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: b80f0667-fe32-41ac-3413-08dac395b02f X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Nov 2022 03:34:49.9148 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: YyWpKQUm9dwGOXAn9ZQvEBur5GrBgB5h6nz4qRGE19+D8ChPSwCGfk6ikbYDNkZCa2z5uLAAoWAIkQ4n53WHyw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR11MB6213 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Hi ALL, Could you please review and provide suggestions if any. Thanks, Mingjin > -----Original Message----- > From: Ye, MingjinX > Sent: 2022=1B$BG/=1B(B11=1B$B7n=1B(B8=1B$BF|=1B(B 21:28 > To: dev@dpdk.org > Cc: Yang, Qiming ; stable@dpdk.org; Zhou, YidingX > ; Ye, MingjinX ; > Richardson, Bruce ; Konstantin Ananyev > ; Zhang, Qi Z ; Lu, > Wenzhuo ; Junyu Jiang ; > Rong, Leyi ; Ajit Khaparde > ; Jerin Jacob ; Xu, > Rosen ; Hemant Agrawal > ; Wisam Jaddo > Subject: [PATCH v5 1/2] net/ice: fix vlan offload >=20 > The vlan tag and flag in Rx descriptor are not processed on vector path, = then > the upper application can't fetch the tci from mbuf. >=20 > This patch is to add handling of vlan RX offloading. >=20 > Fixes: c68a52b8b38c ("net/ice: support vector SSE in Rx") > Fixes: ece1f8a8f1c8 ("net/ice: switch to flexible descriptor in SSE path"= ) > Fixes: 12443386a0b0 ("net/ice: support flex Rx descriptor RxDID22") > Fixes: 214f452f7d5f ("net/ice: add AVX2 offload Rx") > Fixes: 7f85d5ebcfe1 ("net/ice: add AVX512 vector path") > Fixes: 295968d17407 ("ethdev: add namespace") > Fixes: 808a17b3c1e6 ("net/ice: add Rx AVX512 offload path") > Cc: stable@dpdk.org >=20 > Signed-off-by: Mingjin Ye >=20 > v3: > * Fix macros in ice_rxtx_vec_sse.c source file. > v4: > * Fix ice_rx_desc_to_olflags_v define in ice_rxtx_vec_sse.c source > file. > --- > drivers/net/ice/ice_rxtx_vec_avx2.c | 135 +++++++++++++++++----- > drivers/net/ice/ice_rxtx_vec_avx512.c | 154 +++++++++++++++++++++----- > drivers/net/ice/ice_rxtx_vec_sse.c | 132 ++++++++++++++++------ > 3 files changed, 332 insertions(+), 89 deletions(-) >=20 > diff --git a/drivers/net/ice/ice_rxtx_vec_avx2.c > b/drivers/net/ice/ice_rxtx_vec_avx2.c > index 31d6af42fd..bddfd6cf65 100644 > --- a/drivers/net/ice/ice_rxtx_vec_avx2.c > +++ b/drivers/net/ice/ice_rxtx_vec_avx2.c > @@ -474,7 +474,7 @@ _ice_recv_raw_pkts_vec_avx2(struct ice_rx_queue > *rxq, struct rte_mbuf **rx_pkts, > * will cause performance drop to get into this > context. > */ > if (rxq->vsi->adapter->pf.dev_data- > >dev_conf.rxmode.offloads & > - RTE_ETH_RX_OFFLOAD_RSS_HASH) { > + (RTE_ETH_RX_OFFLOAD_RSS_HASH | > RTE_ETH_RX_OFFLOAD_VLAN)) { > /* load bottom half of every 32B desc */ > const __m128i raw_desc_bh7 =3D > _mm_load_si128 > @@ -529,33 +529,112 @@ _ice_recv_raw_pkts_vec_avx2(struct > ice_rx_queue *rxq, struct rte_mbuf **rx_pkts, > * to shift the 32b RSS hash value to the > * highest 32b of each 128b before mask > */ > - __m256i rss_hash6_7 =3D > - _mm256_slli_epi64(raw_desc_bh6_7, > 32); > - __m256i rss_hash4_5 =3D > - _mm256_slli_epi64(raw_desc_bh4_5, > 32); > - __m256i rss_hash2_3 =3D > - _mm256_slli_epi64(raw_desc_bh2_3, > 32); > - __m256i rss_hash0_1 =3D > - _mm256_slli_epi64(raw_desc_bh0_1, > 32); > - > - __m256i rss_hash_msk =3D > - _mm256_set_epi32(0xFFFFFFFF, 0, 0, > 0, > - 0xFFFFFFFF, 0, 0, 0); > - > - rss_hash6_7 =3D _mm256_and_si256 > - (rss_hash6_7, rss_hash_msk); > - rss_hash4_5 =3D _mm256_and_si256 > - (rss_hash4_5, rss_hash_msk); > - rss_hash2_3 =3D _mm256_and_si256 > - (rss_hash2_3, rss_hash_msk); > - rss_hash0_1 =3D _mm256_and_si256 > - (rss_hash0_1, rss_hash_msk); > - > - mb6_7 =3D _mm256_or_si256(mb6_7, > rss_hash6_7); > - mb4_5 =3D _mm256_or_si256(mb4_5, > rss_hash4_5); > - mb2_3 =3D _mm256_or_si256(mb2_3, > rss_hash2_3); > - mb0_1 =3D _mm256_or_si256(mb0_1, > rss_hash0_1); > - } /* if() on RSS hash parsing */ > + if (rxq->vsi->adapter->pf.dev_data- > >dev_conf.rxmode.offloads & > + > RTE_ETH_RX_OFFLOAD_RSS_HASH) { > + __m256i rss_hash6_7 =3D > + > _mm256_slli_epi64(raw_desc_bh6_7, 32); > + __m256i rss_hash4_5 =3D > + > _mm256_slli_epi64(raw_desc_bh4_5, 32); > + __m256i rss_hash2_3 =3D > + > _mm256_slli_epi64(raw_desc_bh2_3, 32); > + __m256i rss_hash0_1 =3D > + > _mm256_slli_epi64(raw_desc_bh0_1, 32); > + > + __m256i rss_hash_msk =3D > + > _mm256_set_epi32(0xFFFFFFFF, 0, 0, 0, > + 0xFFFFFFFF, 0, > 0, 0); > + > + rss_hash6_7 =3D _mm256_and_si256 > + (rss_hash6_7, > rss_hash_msk); > + rss_hash4_5 =3D _mm256_and_si256 > + (rss_hash4_5, > rss_hash_msk); > + rss_hash2_3 =3D _mm256_and_si256 > + (rss_hash2_3, > rss_hash_msk); > + rss_hash0_1 =3D _mm256_and_si256 > + (rss_hash0_1, > rss_hash_msk); > + > + mb6_7 =3D _mm256_or_si256(mb6_7, > rss_hash6_7); > + mb4_5 =3D _mm256_or_si256(mb4_5, > rss_hash4_5); > + mb2_3 =3D _mm256_or_si256(mb2_3, > rss_hash2_3); > + mb0_1 =3D _mm256_or_si256(mb0_1, > rss_hash0_1); > + } /* if() on RSS hash parsing */ > + > + if (rxq->vsi->adapter->pf.dev_data- > >dev_conf.rxmode.offloads & > + > RTE_ETH_RX_OFFLOAD_VLAN) { > + /* merge the status/error-1 bits into > one register */ > + const __m256i status1_4_7 =3D > + > _mm256_unpacklo_epi32(raw_desc_bh6_7, > + raw_desc_bh4_5); > + const __m256i status1_0_3 =3D > + > _mm256_unpacklo_epi32(raw_desc_bh2_3, > + raw_desc_bh0_1); > + > + const __m256i status1_0_7 =3D > + > _mm256_unpacklo_epi64(status1_4_7, > + status1_0_3); > + > + const __m256i l2tag2p_flag_mask =3D > + > _mm256_set1_epi32(1 << 11); > + > + __m256i l2tag2p_flag_bits =3D > + _mm256_and_si256 > + (status1_0_7, > l2tag2p_flag_mask); > + > + l2tag2p_flag_bits =3D > + > _mm256_srli_epi32(l2tag2p_flag_bits, > + 11); > + > + __m256i vlan_flags =3D > _mm256_setzero_si256(); > + const __m256i l2tag2_flags_shuf =3D > + _mm256_set_epi8(0, > 0, 0, 0, > + 0, 0, 0, > 0, > + 0, 0, 0, > 0, > + 0, 0, 0, > 0, > + /* > end up 128-bits */ > + 0, 0, 0, > 0, > + 0, 0, 0, > 0, > + 0, 0, 0, > 0, > + 0, 0, > + > RTE_MBUF_F_RX_VLAN | > + > RTE_MBUF_F_RX_VLAN_STRIPPED, > + 0); > + vlan_flags =3D > + > _mm256_shuffle_epi8(l2tag2_flags_shuf, > + l2tag2p_flag_bits); > + > + /* merge with vlan_flags */ > + mbuf_flags =3D _mm256_or_si256 > + (mbuf_flags, > vlan_flags); > + > + /* L2TAG2_2 */ > + __m256i vlan_tci6_7 =3D > + > _mm256_slli_si256(raw_desc_bh6_7, 4); > + __m256i vlan_tci4_5 =3D > + > _mm256_slli_si256(raw_desc_bh4_5, 4); > + __m256i vlan_tci2_3 =3D > + > _mm256_slli_si256(raw_desc_bh2_3, 4); > + __m256i vlan_tci0_1 =3D > + > _mm256_slli_si256(raw_desc_bh0_1, 4); > + > + const __m256i vlan_tci_msk =3D > + _mm256_set_epi32(0, > 0xFFFF0000, 0, 0, > + 0, 0xFFFF0000, 0, 0); > + > + vlan_tci6_7 =3D _mm256_and_si256 > + > (vlan_tci6_7, vlan_tci_msk); > + vlan_tci4_5 =3D _mm256_and_si256 > + > (vlan_tci4_5, vlan_tci_msk); > + vlan_tci2_3 =3D _mm256_and_si256 > + > (vlan_tci2_3, vlan_tci_msk); > + vlan_tci0_1 =3D _mm256_and_si256 > + > (vlan_tci0_1, vlan_tci_msk); > + > + mb6_7 =3D _mm256_or_si256(mb6_7, > vlan_tci6_7); > + mb4_5 =3D _mm256_or_si256(mb4_5, > vlan_tci4_5); > + mb2_3 =3D _mm256_or_si256(mb2_3, > vlan_tci2_3); > + mb0_1 =3D _mm256_or_si256(mb0_1, > vlan_tci0_1); > + } > + } > #endif > } >=20 > diff --git a/drivers/net/ice/ice_rxtx_vec_avx512.c > b/drivers/net/ice/ice_rxtx_vec_avx512.c > index 5bfd5152df..5d5e4bf3cd 100644 > --- a/drivers/net/ice/ice_rxtx_vec_avx512.c > +++ b/drivers/net/ice/ice_rxtx_vec_avx512.c > @@ -585,7 +585,7 @@ _ice_recv_raw_pkts_vec_avx512(struct > ice_rx_queue *rxq, > * will cause performance drop to get into this > context. > */ > if (rxq->vsi->adapter->pf.dev_data- > >dev_conf.rxmode.offloads & > - RTE_ETH_RX_OFFLOAD_RSS_HASH) { > + (RTE_ETH_RX_OFFLOAD_RSS_HASH | > RTE_ETH_RX_OFFLOAD_VLAN)) { > /* load bottom half of every 32B desc */ > const __m128i raw_desc_bh7 =3D > _mm_load_si128 > @@ -640,33 +640,131 @@ _ice_recv_raw_pkts_vec_avx512(struct > ice_rx_queue *rxq, > * to shift the 32b RSS hash value to the > * highest 32b of each 128b before mask > */ > - __m256i rss_hash6_7 =3D > - _mm256_slli_epi64(raw_desc_bh6_7, > 32); > - __m256i rss_hash4_5 =3D > - _mm256_slli_epi64(raw_desc_bh4_5, > 32); > - __m256i rss_hash2_3 =3D > - _mm256_slli_epi64(raw_desc_bh2_3, > 32); > - __m256i rss_hash0_1 =3D > - _mm256_slli_epi64(raw_desc_bh0_1, > 32); > - > - __m256i rss_hash_msk =3D > - _mm256_set_epi32(0xFFFFFFFF, 0, 0, > 0, > - 0xFFFFFFFF, 0, 0, 0); > - > - rss_hash6_7 =3D _mm256_and_si256 > - (rss_hash6_7, rss_hash_msk); > - rss_hash4_5 =3D _mm256_and_si256 > - (rss_hash4_5, rss_hash_msk); > - rss_hash2_3 =3D _mm256_and_si256 > - (rss_hash2_3, rss_hash_msk); > - rss_hash0_1 =3D _mm256_and_si256 > - (rss_hash0_1, rss_hash_msk); > - > - mb6_7 =3D _mm256_or_si256(mb6_7, > rss_hash6_7); > - mb4_5 =3D _mm256_or_si256(mb4_5, > rss_hash4_5); > - mb2_3 =3D _mm256_or_si256(mb2_3, > rss_hash2_3); > - mb0_1 =3D _mm256_or_si256(mb0_1, > rss_hash0_1); > - } /* if() on RSS hash parsing */ > + if (rxq->vsi->adapter->pf.dev_data- > >dev_conf.rxmode.offloads & > + > RTE_ETH_RX_OFFLOAD_RSS_HASH) { > + __m256i rss_hash6_7 =3D > + > _mm256_slli_epi64(raw_desc_bh6_7, 32); > + __m256i rss_hash4_5 =3D > + > _mm256_slli_epi64(raw_desc_bh4_5, 32); > + __m256i rss_hash2_3 =3D > + > _mm256_slli_epi64(raw_desc_bh2_3, 32); > + __m256i rss_hash0_1 =3D > + > _mm256_slli_epi64(raw_desc_bh0_1, 32); > + > + __m256i rss_hash_msk =3D > + > _mm256_set_epi32(0xFFFFFFFF, 0, 0, 0, > + 0xFFFFFFFF, 0, > 0, 0); > + > + rss_hash6_7 =3D _mm256_and_si256 > + (rss_hash6_7, > rss_hash_msk); > + rss_hash4_5 =3D _mm256_and_si256 > + (rss_hash4_5, > rss_hash_msk); > + rss_hash2_3 =3D _mm256_and_si256 > + (rss_hash2_3, > rss_hash_msk); > + rss_hash0_1 =3D _mm256_and_si256 > + (rss_hash0_1, > rss_hash_msk); > + > + mb6_7 =3D _mm256_or_si256(mb6_7, > rss_hash6_7); > + mb4_5 =3D _mm256_or_si256(mb4_5, > rss_hash4_5); > + mb2_3 =3D _mm256_or_si256(mb2_3, > rss_hash2_3); > + mb0_1 =3D _mm256_or_si256(mb0_1, > rss_hash0_1); > + } /* if() on RSS hash parsing */ > + > + if (rxq->vsi->adapter->pf.dev_data- > >dev_conf.rxmode.offloads & > + > RTE_ETH_RX_OFFLOAD_VLAN) { > + /* merge the status/error-1 bits into > one register */ > + const __m256i status1_4_7 =3D > + _mm256_unpacklo_epi32 > + (raw_desc_bh6_7, > + raw_desc_bh4_5); > + const __m256i status1_0_3 =3D > + _mm256_unpacklo_epi32 > + (raw_desc_bh2_3, > + raw_desc_bh0_1); > + > + const __m256i status1_0_7 =3D > + _mm256_unpacklo_epi64 > + (status1_4_7, status1_0_3); > + > + const __m256i l2tag2p_flag_mask =3D > + _mm256_set1_epi32 > + (1 << 11); > + > + __m256i l2tag2p_flag_bits =3D > + _mm256_and_si256 > + (status1_0_7, > + l2tag2p_flag_mask); > + > + l2tag2p_flag_bits =3D > + _mm256_srli_epi32 > + (l2tag2p_flag_bits, > + 11); > + const __m256i l2tag2_flags_shuf =3D > + _mm256_set_epi8 > + (0, 0, 0, 0, > + 0, 0, 0, 0, > + 0, 0, 0, 0, > + 0, 0, 0, 0, > + /* end up 128-bits */ > + 0, 0, 0, 0, > + 0, 0, 0, 0, > + 0, 0, 0, 0, > + 0, 0, > + > RTE_MBUF_F_RX_VLAN | > + > RTE_MBUF_F_RX_VLAN_STRIPPED, > + 0); > + __m256i vlan_flags =3D > + _mm256_shuffle_epi8 > + (l2tag2_flags_shuf, > + l2tag2p_flag_bits); > + > + /* merge with vlan_flags */ > + mbuf_flags =3D _mm256_or_si256 > + (mbuf_flags, > + vlan_flags); > + > + /* L2TAG2_2 */ > + __m256i vlan_tci6_7 =3D > + _mm256_slli_si256 > + (raw_desc_bh6_7, 4); > + __m256i vlan_tci4_5 =3D > + _mm256_slli_si256 > + (raw_desc_bh4_5, 4); > + __m256i vlan_tci2_3 =3D > + _mm256_slli_si256 > + (raw_desc_bh2_3, 4); > + __m256i vlan_tci0_1 =3D > + _mm256_slli_si256 > + (raw_desc_bh0_1, 4); > + > + const __m256i vlan_tci_msk =3D > + _mm256_set_epi32 > + (0, 0xFFFF0000, 0, 0, > + 0, 0xFFFF0000, 0, 0); > + > + vlan_tci6_7 =3D _mm256_and_si256 > + (vlan_tci6_7, > + vlan_tci_msk); > + vlan_tci4_5 =3D _mm256_and_si256 > + (vlan_tci4_5, > + vlan_tci_msk); > + vlan_tci2_3 =3D _mm256_and_si256 > + (vlan_tci2_3, > + vlan_tci_msk); > + vlan_tci0_1 =3D _mm256_and_si256 > + (vlan_tci0_1, > + vlan_tci_msk); > + > + mb6_7 =3D _mm256_or_si256 > + (mb6_7, vlan_tci6_7); > + mb4_5 =3D _mm256_or_si256 > + (mb4_5, vlan_tci4_5); > + mb2_3 =3D _mm256_or_si256 > + (mb2_3, vlan_tci2_3); > + mb0_1 =3D _mm256_or_si256 > + (mb0_1, vlan_tci0_1); > + } > + } > #endif > } >=20 > diff --git a/drivers/net/ice/ice_rxtx_vec_sse.c > b/drivers/net/ice/ice_rxtx_vec_sse.c > index fd94cedde3..cc5b8510dc 100644 > --- a/drivers/net/ice/ice_rxtx_vec_sse.c > +++ b/drivers/net/ice/ice_rxtx_vec_sse.c > @@ -100,9 +100,15 @@ ice_rxq_rearm(struct ice_rx_queue *rxq) > ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id); } >=20 > +#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC > +static inline void > +ice_rx_desc_to_olflags_v(struct ice_rx_queue *rxq, __m128i descs[4], > __m128i descs_bh[4], > + struct rte_mbuf **rx_pkts) > +#else > static inline void > ice_rx_desc_to_olflags_v(struct ice_rx_queue *rxq, __m128i descs[4], > struct rte_mbuf **rx_pkts) > +#endif > { > const __m128i mbuf_init =3D _mm_set_epi64x(0, rxq- > >mbuf_initializer); > __m128i rearm0, rearm1, rearm2, rearm3; @@ -214,6 +220,38 @@ > ice_rx_desc_to_olflags_v(struct ice_rx_queue *rxq, __m128i descs[4], > /* merge the flags */ > flags =3D _mm_or_si128(flags, rss_vlan); >=20 > + #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC > + if (rxq->vsi->adapter->pf.dev_data->dev_conf.rxmode.offloads & > + > RTE_ETH_RX_OFFLOAD_VLAN) { > + const __m128i l2tag2_mask =3D > + _mm_set1_epi32(1 << 11); > + const __m128i vlan_tci0_1 =3D > + _mm_unpacklo_epi32(descs_bh[0], descs_bh[1]); > + const __m128i vlan_tci2_3 =3D > + _mm_unpacklo_epi32(descs_bh[2], descs_bh[3]); > + const __m128i vlan_tci0_3 =3D > + _mm_unpacklo_epi64(vlan_tci0_1, vlan_tci2_3); > + > + __m128i vlan_bits =3D _mm_and_si128(vlan_tci0_3, > l2tag2_mask); > + > + vlan_bits =3D _mm_srli_epi32(vlan_bits, 11); > + > + const __m128i vlan_flags_shuf =3D > + _mm_set_epi8(0, 0, 0, 0, > + 0, 0, 0, 0, > + 0, 0, 0, 0, > + 0, 0, > + RTE_MBUF_F_RX_VLAN | > + RTE_MBUF_F_RX_VLAN_STRIPPED, > + 0); > + > + const __m128i vlan_flags =3D > _mm_shuffle_epi8(vlan_flags_shuf, > +vlan_bits); > + > + /* merge with vlan_flags */ > + flags =3D _mm_or_si128(flags, vlan_flags); > + } > +#endif > + > if (rxq->fdir_enabled) { > const __m128i fdir_id0_1 =3D > _mm_unpackhi_epi32(descs[0], descs[1]); @@ - > 405,6 +443,9 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct > rte_mbuf **rx_pkts, > pos +=3D ICE_DESCS_PER_LOOP, > rxdp +=3D ICE_DESCS_PER_LOOP) { > __m128i descs[ICE_DESCS_PER_LOOP]; > + #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC > + __m128i descs_bh[ICE_DESCS_PER_LOOP]; > + #endif > __m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3; > __m128i staterr, sterr_tmp1, sterr_tmp2; > /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */ @@ - > 463,8 +504,6 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct > rte_mbuf **rx_pkts, > /* C.1 4=3D>2 filter staterr info only */ > sterr_tmp1 =3D _mm_unpackhi_epi32(descs[1], descs[0]); >=20 > - ice_rx_desc_to_olflags_v(rxq, descs, &rx_pkts[pos]); > - > /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */ > pkt_mb3 =3D _mm_add_epi16(pkt_mb3, crc_adjust); > pkt_mb2 =3D _mm_add_epi16(pkt_mb2, crc_adjust); @@ - > 479,21 +518,21 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, > struct rte_mbuf **rx_pkts, > * will cause performance drop to get into this context. > */ > if (rxq->vsi->adapter->pf.dev_data- > >dev_conf.rxmode.offloads & > - RTE_ETH_RX_OFFLOAD_RSS_HASH) { > + (RTE_ETH_RX_OFFLOAD_RSS_HASH | > RTE_ETH_RX_OFFLOAD_VLAN)) { > /* load bottom half of every 32B desc */ > - const __m128i raw_desc_bh3 =3D > + descs_bh[3] =3D > _mm_load_si128 > ((void > *)(&rxdp[3].wb.status_error1)); > rte_compiler_barrier(); > - const __m128i raw_desc_bh2 =3D > + descs_bh[2] =3D > _mm_load_si128 > ((void > *)(&rxdp[2].wb.status_error1)); > rte_compiler_barrier(); > - const __m128i raw_desc_bh1 =3D > + descs_bh[1] =3D > _mm_load_si128 > ((void > *)(&rxdp[1].wb.status_error1)); > rte_compiler_barrier(); > - const __m128i raw_desc_bh0 =3D > + descs_bh[0] =3D > _mm_load_si128 > ((void > *)(&rxdp[0].wb.status_error1)); >=20 > @@ -501,32 +540,59 @@ _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, > struct rte_mbuf **rx_pkts, > * to shift the 32b RSS hash value to the > * highest 32b of each 128b before mask > */ > - __m128i rss_hash3 =3D > - _mm_slli_epi64(raw_desc_bh3, 32); > - __m128i rss_hash2 =3D > - _mm_slli_epi64(raw_desc_bh2, 32); > - __m128i rss_hash1 =3D > - _mm_slli_epi64(raw_desc_bh1, 32); > - __m128i rss_hash0 =3D > - _mm_slli_epi64(raw_desc_bh0, 32); > - > - __m128i rss_hash_msk =3D > - _mm_set_epi32(0xFFFFFFFF, 0, 0, 0); > - > - rss_hash3 =3D _mm_and_si128 > - (rss_hash3, rss_hash_msk); > - rss_hash2 =3D _mm_and_si128 > - (rss_hash2, rss_hash_msk); > - rss_hash1 =3D _mm_and_si128 > - (rss_hash1, rss_hash_msk); > - rss_hash0 =3D _mm_and_si128 > - (rss_hash0, rss_hash_msk); > - > - pkt_mb3 =3D _mm_or_si128(pkt_mb3, rss_hash3); > - pkt_mb2 =3D _mm_or_si128(pkt_mb2, rss_hash2); > - pkt_mb1 =3D _mm_or_si128(pkt_mb1, rss_hash1); > - pkt_mb0 =3D _mm_or_si128(pkt_mb0, rss_hash0); > - } /* if() on RSS hash parsing */ > + if (rxq->vsi->adapter->pf.dev_data- > >dev_conf.rxmode.offloads & > + > RTE_ETH_RX_OFFLOAD_RSS_HASH) { > + __m128i rss_hash3 =3D > + _mm_slli_epi64(descs_bh[3], 32); > + __m128i rss_hash2 =3D > + _mm_slli_epi64(descs_bh[2], 32); > + __m128i rss_hash1 =3D > + _mm_slli_epi64(descs_bh[1], 32); > + __m128i rss_hash0 =3D > + _mm_slli_epi64(descs_bh[0], 32); > + > + __m128i rss_hash_msk =3D > + _mm_set_epi32(0xFFFFFFFF, 0, 0, 0); > + > + rss_hash3 =3D _mm_and_si128 > + (rss_hash3, rss_hash_msk); > + rss_hash2 =3D _mm_and_si128 > + (rss_hash2, rss_hash_msk); > + rss_hash1 =3D _mm_and_si128 > + (rss_hash1, rss_hash_msk); > + rss_hash0 =3D _mm_and_si128 > + (rss_hash0, rss_hash_msk); > + > + pkt_mb3 =3D _mm_or_si128(pkt_mb3, > rss_hash3); > + pkt_mb2 =3D _mm_or_si128(pkt_mb2, > rss_hash2); > + pkt_mb1 =3D _mm_or_si128(pkt_mb1, > rss_hash1); > + pkt_mb0 =3D _mm_or_si128(pkt_mb0, > rss_hash0); > + } /* if() on RSS hash parsing */ > + > + if (rxq->vsi->adapter->pf.dev_data- > >dev_conf.rxmode.offloads & > + > RTE_ETH_RX_OFFLOAD_VLAN) { > + /* > L2TAG2_2 */ > + __m128i vlan_tci3 =3D > _mm_slli_si128(descs_bh[3], 4); > + __m128i vlan_tci2 =3D > _mm_slli_si128(descs_bh[2], 4); > + __m128i vlan_tci1 =3D > _mm_slli_si128(descs_bh[1], 4); > + __m128i vlan_tci0 =3D > _mm_slli_si128(descs_bh[0], 4); > + > + const __m128i vlan_tci_msk =3D > _mm_set_epi32(0, 0xFFFF0000, 0, 0); > + > + vlan_tci3 =3D _mm_and_si128(vlan_tci3, > vlan_tci_msk); > + vlan_tci2 =3D _mm_and_si128(vlan_tci2, > vlan_tci_msk); > + vlan_tci1 =3D _mm_and_si128(vlan_tci1, > vlan_tci_msk); > + vlan_tci0 =3D _mm_and_si128(vlan_tci0, > vlan_tci_msk); > + > + pkt_mb3 =3D _mm_or_si128(pkt_mb3, > vlan_tci3); > + pkt_mb2 =3D _mm_or_si128(pkt_mb2, > vlan_tci2); > + pkt_mb1 =3D _mm_or_si128(pkt_mb1, > vlan_tci1); > + pkt_mb0 =3D _mm_or_si128(pkt_mb0, > vlan_tci0); > + } > + ice_rx_desc_to_olflags_v(rxq, descs, descs_bh, > &rx_pkts[pos]); > + } > +#else > + ice_rx_desc_to_olflags_v(rxq, descs, &rx_pkts[pos]); > #endif >=20 > /* C.2 get 4 pkts staterr value */ > -- > 2.34.1