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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CY8PR11MB7747.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 63f67e6c-9123-4634-e2be-08dd50a77c13 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Feb 2025 05:37:22.7291 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: CcS4pVQaB64iU+Xq18WnRKsiietMfQ64Ot4eUXok2dbFwTLpv9mHBbNWnMotO6TT4eVkG0hPZRScChBDKmJ/qnKxKPSB3TL848j13aUsqJs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR11MB6540 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Wed, Feb 12, 2025 at 09:47:11PM +0000, Soumyadeep Hore wrote: > Enabling Tx timestamp queue for supporting Tx time based scheduling of=20 > packets. >=20 Can you provide more details of this feature and how it can be used, how it= is enabled/disabled etc. See also comments inline below. /Bruce > Signed-off-by: Soumyadeep Hore > --- > drivers/net/intel/common/tx.h | 5 + > drivers/net/intel/ice/base/ice_lan_tx_rx.h | 1 + > drivers/net/intel/ice/ice_ethdev.h | 1 + > drivers/net/intel/ice/ice_rxtx.c | 174 +++++++++++++++++++++ > drivers/net/intel/ice/ice_rxtx.h | 5 + > 5 files changed, 186 insertions(+) >=20 > diff --git a/drivers/net/intel/common/tx.h=20 > b/drivers/net/intel/common/tx.h index d9cf4474fc..f3777fa9e7 100644 > --- a/drivers/net/intel/common/tx.h > +++ b/drivers/net/intel/common/tx.h > @@ -35,6 +35,7 @@ struct ci_tx_queue { > volatile struct i40e_tx_desc *i40e_tx_ring; > volatile struct iavf_tx_desc *iavf_tx_ring; > volatile struct ice_tx_desc *ice_tx_ring; > + volatile struct ice_ts_desc *ice_tstamp_ring; This code looks a bit strange to me, can you please check my understanding = of it is correct. This is a union, so the time stamp ring here is replacing the whole descrip= tor ring for the queue? Therefore, we will have some queues which have regu= lar descriptors and others which have only timestamp descriptors. Is that correct? Another minor point is that this union has the elements in alphabetical ord= er, so ice_ts_desc needs to come before ice_tx_desc. > volatile union ixgbe_adv_tx_desc *ixgbe_tx_ring; > }; > volatile uint8_t *qtx_tail; /* register address of tail *= / > @@ -76,6 +77,10 @@ struct ci_tx_queue { > union { > struct { /* ICE driver specific values */ > uint32_t q_teid; /* TX schedule node id. */ > + uint16_t nb_tstamp_desc; /* number of Timestamp descriptors */ > + volatile uint8_t *tstamp_tail; /* value of timestamp tail register */ > + rte_iova_t tstamp_ring_dma; /* Timestamp ring DMA address */ > + uint16_t next_tstamp_id; You are adding lots of holes into the structure here, please reorder the fi= elds to reduce the space used by the structure. Also, do you need the field tstamp_tail? Since ice_tstamp_ring is replacing= ice_tx_ring in the union above, you should be able to just reuse the exist= ing tail register for this, no? Similarly for tstamp_ring_dma, can the existing dma address field not be us= ed. OVerall, I think rather than expanding out our common tx queue structure, i= t may be better to have the queue structure hold a pointer to another separ= ate tx timestamp structure, allocated separately. Hi Bruce only one Tx ring is available for multiple Tx queues so we need se= parate DMA and tail. > }; > struct { /* I40E driver specific values */ > uint8_t dcb_tc; > diff --git a/drivers/net/intel/ice/base/ice_lan_tx_rx.h=20 > b/drivers/net/intel/ice/base/ice_lan_tx_rx.h > index 940c6843d9..edd1137114 100644 > --- a/drivers/net/intel/ice/base/ice_lan_tx_rx.h > +++ b/drivers/net/intel/ice/base/ice_lan_tx_rx.h > @@ -1279,6 +1279,7 @@ struct ice_ts_desc { > #define ICE_SET_TXTIME_MAX_Q_AMOUNT 127 > #define ICE_OP_TXTIME_MAX_Q_AMOUNT 2047 > #define ICE_TXTIME_FETCH_TS_DESC_DFLT 8 > +#define ICE_TXTIME_FETCH_PROFILE_CNT 16 > =20 > /* Tx Time queue context data > * This base code update, adding a define, should be in the previous patch whe= re all the other base code defines are added. > diff --git a/drivers/net/intel/ice/ice_ethdev.h=20 > b/drivers/net/intel/ice/ice_ethdev.h > index afe8dae497..9649456771 100644 > --- a/drivers/net/intel/ice/ice_ethdev.h > +++ b/drivers/net/intel/ice/ice_ethdev.h > @@ -299,6 +299,7 @@ struct ice_vsi { > uint8_t enabled_tc; /* The traffic class enabled */ > uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */ > uint8_t vlan_filter_on; /* The VLAN filter enabled */ > + uint8_t enabled_txpp; /* TXPP support enabled */ While I realise that "enabled_txpp" matches the "enabled_tc" variable above= , it would read better as "txpp_enabled". You could also have it align to t= he previous two members, perhaps: would it work calling it "txpp_on". > /* information about rss configuration */ > u32 rss_key_size; > u32 rss_lut_size; > diff --git a/drivers/net/intel/ice/ice_rxtx.c=20 > b/drivers/net/intel/ice/ice_rxtx.c > index 8dd8644b16..f043ae3aa6 100644 > --- a/drivers/net/intel/ice/ice_rxtx.c > +++ b/drivers/net/intel/ice/ice_rxtx.c > @@ -5,6 +5,7 @@ > #include > #include > #include > +#include > =20 > #include "ice_rxtx.h" > #include "ice_rxtx_vec_common.h" > @@ -741,6 +742,87 @@ ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t = rx_queue_id) > return 0; > } > =20 > +/** > + * ice_setup_txtime_ctx - setup a struct ice_txtime_ctx instance > + * @ring: The tstamp ring to configure > + * @txtime_ctx: Pointer to the Tx time queue context structure to be=20 > +initialized > + * @txtime_ena: Tx time enable flag, set to true if Tx time should be=20 > +enabled */ static int ice_setup_txtime_ctx(struct ci_tx_queue *txq, > + struct ice_txtime_ctx *txtime_ctx, bool txtime_ena) { > + struct ice_vsi *vsi =3D txq->ice_vsi; > + struct ice_hw *hw; > + > + hw =3D ICE_VSI_TO_HW(vsi); > + txtime_ctx->base =3D txq->tstamp_ring_dma >>=20 > +ICE_TX_CMPLTNQ_CTX_BASE_S; > + > + /* Tx time Queue Length */ > + txtime_ctx->qlen =3D txq->nb_tstamp_desc; > + > + if (txtime_ena) > + txtime_ctx->txtime_ena_q =3D 1; > + > + /* PF number */ > + txtime_ctx->pf_num =3D hw->pf_id; > + > + switch (vsi->type) { > + case ICE_VSI_LB: > + case ICE_VSI_CTRL: > + case ICE_VSI_ADI: > + case ICE_VSI_PF: > + txtime_ctx->vmvf_type =3D ICE_TLAN_CTX_VMVF_TYPE_PF; > + break; > + default: > + PMD_DRV_LOG(ERR, "Unable to set VMVF type for VSI type %d", > + vsi->type); > + return -EINVAL; > + } > + > + /* make sure the context is associated with the right VSI */ > + txtime_ctx->src_vsi =3D ice_get_hw_vsi_num(hw, vsi->idx); > + > + > + txtime_ctx->ts_res =3D ICE_TXTIME_CTX_RESOLUTION_128NS; > + txtime_ctx->drbell_mode_32 =3D ICE_TXTIME_CTX_DRBELL_MODE_32; > + txtime_ctx->ts_fetch_prof_id =3D ICE_TXTIME_CTX_FETCH_PROF_ID_0; > + > + return 0; > +} > + > +/** > + * ice_calc_ts_ring_count - Calculate the number of timestamp=20 > +descriptors > + * @hw: pointer to the hardware structure > + * @tx_desc_count: number of Tx descriptors in the ring > + * > + * Return: the number of timestamp descriptors */ uint16_t=20 > +ice_calc_ts_ring_count(struct ice_hw *hw, u16 tx_desc_count) { > + uint16_t prof =3D ICE_TXTIME_CTX_FETCH_PROF_ID_0; > + uint16_t max_fetch_desc =3D 0; > + uint16_t fetch; > + uint32_t reg; > + uint16_t i; > + > + for (i =3D 0; i < ICE_TXTIME_FETCH_PROFILE_CNT; i++) { > + reg =3D rd32(hw, E830_GLTXTIME_FETCH_PROFILE(prof, 0)); > + fetch =3D ((uint32_t)((reg & > + E830_GLTXTIME_FETCH_PROFILE_FETCH_TS_DESC_M) > + >> rte_bsf64 > + (E830_GLTXTIME_FETCH_PROFILE_FETCH_TS_DESC_M))); > + max_fetch_desc =3D max(fetch, max_fetch_desc); > + } > + > + if (!max_fetch_desc) > + max_fetch_desc =3D ICE_TXTIME_FETCH_TS_DESC_DFLT; > + > + max_fetch_desc =3D RTE_ALIGN(max_fetch_desc, ICE_REQ_DESC_MULTIPLE); > + > + return tx_desc_count + max_fetch_desc; } > + > int > ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) {=20 > @@ -829,6 +911,29 @@ ice_tx_queue_start(struct rte_eth_dev *dev,=20 > uint16_t tx_queue_id) > =20 > dev->data->tx_queue_state[tx_queue_id] =3D=20 > RTE_ETH_QUEUE_STATE_STARTED; > =20 > + if (txq->ice_tstamp_ring) { Is this meant to be a check for timestamping enabled? Suggest changing to c= heck the enabled_txpp variable instead, because this condition will be true= for a regular TX ring as well, since the descriptor ring pointer will be n= on-null. Same comment applied below also. > + struct ice_aqc_set_txtime_qgrp *txtime_qg_buf; > + u8 txtime_buf_len =3D ice_struct_size(txtime_qg_buf, txtimeqs, 1); > + struct ice_txtime_ctx txtime_ctx =3D { 0 }; > + > + txtime_qg_buf =3D ice_malloc(hw, txtime_buf_len); > + ice_setup_txtime_ctx(txq, &txtime_ctx, > + vsi->enabled_txpp); > + ice_set_ctx(hw, (u8 *)&txtime_ctx, > + txtime_qg_buf->txtimeqs[0].txtime_ctx, > + ice_txtime_ctx_info); > + > + txq->tstamp_tail =3D hw->hw_addr + > + E830_GLQTX_TXTIME_DBELL_LSB(tx_queue_id); > + > + err =3D ice_aq_set_txtimeq(hw, tx_queue_id, 1, txtime_qg_buf, > + txtime_buf_len, NULL); > + if (err) { > + PMD_DRV_LOG(ERR, "Failed to set Tx Time queue context, error: %d", er= r); > + return err; > + } > + } > + > rte_free(txq_elem); > return 0; > } > @@ -1039,6 +1144,22 @@ ice_reset_tx_queue(struct ci_tx_queue *txq) > prev =3D i; > } > =20 > + if (txq->ice_tstamp_ring) { > + size =3D sizeof(struct ice_ts_desc) * txq->nb_tstamp_desc; > + for (i =3D 0; i < size; i++) > + ((volatile char *)txq->ice_tstamp_ring)[i] =3D 0; > + > + prev =3D (uint16_t)(txq->nb_tstamp_desc - 1); > + for (i =3D 0; i < txq->nb_tstamp_desc; i++) { > + volatile struct ice_ts_desc *tsd =3D &txq->ice_tstamp_ring[i]; > + tsd->tx_desc_idx_tstamp =3D 0; > + prev =3D i; > + } > + > + txq->next_tstamp_id =3D 0; > + txq->tstamp_tail =3D NULL; > + } > + > txq->tx_next_dd =3D (uint16_t)(txq->tx_rs_thresh - 1); > txq->tx_next_rs =3D (uint16_t)(txq->tx_rs_thresh - 1); > =20 > @@ -1501,6 +1622,24 @@ ice_tx_queue_setup(struct rte_eth_dev *dev, > return -ENOMEM; > } > =20 > + if (vsi->type =3D=3D ICE_VSI_PF && vsi->enabled_txpp) { > + const struct rte_memzone *tstamp_z =3D > + rte_eth_dma_zone_reserve(dev, "ice_tstamp_ring", > + queue_idx, ring_size, ICE_RING_BASE_ALIGN, > + socket_id); > + if (!tstamp_z) { > + ice_tx_queue_release(txq); > + PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX"); > + return -ENOMEM; > + } > + > + txq->nb_tstamp_desc =3D > + ice_calc_ts_ring_count(ICE_VSI_TO_HW(vsi), > + txq->nb_tx_desc); > + } else { > + txq->ice_tstamp_ring =3D NULL; > + } > + > ice_reset_tx_queue(txq); > txq->q_set =3D true; > dev->data->tx_queues[queue_idx] =3D txq; @@ -3161,6 +3300,41 @@=20 > ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts= ) > txd->cmd_type_offset_bsz |=3D > rte_cpu_to_le_64(((uint64_t)td_cmd) << > ICE_TXD_QW1_CMD_S); > + > + if (txq->ice_tstamp_ring) { > + volatile struct ice_ts_desc *ts_desc; > + volatile struct ice_ts_desc *ice_tstamp_ring; > + struct timespec sys_time; > + uint16_t next_ts_id =3D txq->next_tstamp_id; > + uint64_t ns; > + uint32_t tstamp; > + > + clock_gettime(CLOCK_REALTIME, &sys_time); > + ns =3D rte_timespec_to_ns(&sys_time); > + tstamp =3D ns >> ICE_TXTIME_CTX_RESOLUTION_128NS; > + > + ice_tstamp_ring =3D txq->ice_tstamp_ring; > + ts_desc =3D &ice_tstamp_ring[next_ts_id]; > + ts_desc->tx_desc_idx_tstamp =3D > + rte_cpu_to_le_32(((uint32_t)tx_id & > + ICE_TXTIME_TX_DESC_IDX_M) | > + ((uint32_t)tstamp << ICE_TXTIME_STAMP_M)); > + > + next_ts_id++; > + if (next_ts_id =3D=3D txq->nb_tstamp_desc) { > + int fetch =3D txq->nb_tstamp_desc - txq->nb_tx_desc; > + > + for (next_ts_id =3D 0; next_ts_id < fetch; next_ts_id++) { > + ts_desc =3D &ice_tstamp_ring[next_ts_id]; > + ts_desc->tx_desc_idx_tstamp =3D > + rte_cpu_to_le_32(((uint32_t)tx_id & > + ICE_TXTIME_TX_DESC_IDX_M) | > + ((uint32_t)tstamp << ICE_TXTIME_STAMP_M)); > + } > + } > + txq->next_tstamp_id =3D next_ts_id; > + ICE_PCI_REG_WRITE(txq->tstamp_tail, next_ts_id); > + } > } > end_of_tx: > /* update Tail register */ > diff --git a/drivers/net/intel/ice/ice_rxtx.h=20 > b/drivers/net/intel/ice/ice_rxtx.h > index f9293ac6f9..651e146e6d 100644 > --- a/drivers/net/intel/ice/ice_rxtx.h > +++ b/drivers/net/intel/ice/ice_rxtx.h > @@ -29,6 +29,10 @@ > #define ice_rx_flex_desc ice_32b_rx_flex_desc #endif > =20 > +#define ICE_TXTIME_TX_DESC_IDX_M 0x00001fff > +#define ICE_TXTIME_STAMP_M 12 > +#define ICE_REQ_DESC_MULTIPLE 32 > + > #define ICE_SUPPORT_CHAIN_NUM 5 > =20 > #define ICE_TD_CMD ICE_TX_DESC_CMD_EOP > @@ -293,6 +297,7 @@ uint16_t ice_xmit_pkts_vec_avx512_offload(void=20 > *tx_queue, int ice_fdir_programming(struct ice_pf *pf, struct=20 > ice_fltr_desc *fdir_desc); int ice_tx_done_cleanup(void *txq,=20 > uint32_t free_cnt); int ice_get_monitor_addr(void *rx_queue, struct=20 > rte_power_monitor_cond *pmc); > +u16 ice_calc_ts_ring_count(struct ice_hw *hw, u16 tx_desc_count); > =20 > #define FDIR_PARSING_ENABLE_PER_QUEUE(ad, on) do { \ > int i; \ > -- > 2.43.0 >=20