From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-f180.google.com (mail-pf0-f180.google.com [209.85.192.180]) by dpdk.org (Postfix) with ESMTP id 6AE2B98 for ; Tue, 10 Jan 2017 03:47:24 +0100 (CET) Received: by mail-pf0-f180.google.com with SMTP id 189so25665999pfu.3 for ; Mon, 09 Jan 2017 18:47:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=purestorage.com; s=google; h=mime-version:subject:from:in-reply-to:date :content-transfer-encoding:message-id:references:to; bh=lbE3HbM6XLisFkAVeLlOndIupJKOPuRIb/kBssSxT6g=; b=NwJjY0h9mDgyy9urgah+BEtSrxbMzR2zV1lxJBMCSjJO4JIJAZUWy3N4kL2YXv247+ uY1zN3Xkbtr0Rq4ksYGGx72JBAusS74rhzrYfFdOXfm+mPj0ukb1TJxijQXGI845ldDy zl/uiETduZKvv9eULCuANX9YDDHdKXKfniVEw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:subject:from:in-reply-to:date :content-transfer-encoding:message-id:references:to; bh=lbE3HbM6XLisFkAVeLlOndIupJKOPuRIb/kBssSxT6g=; b=ZQt4MIQmPBYjRhcz66ToWYBR/Z9BeP74FWITzInKrNMJyF4qlIfOjbIEOtNEWRMbFu rZJcR5GhybS4fQXEttYL2iSHEAcBT0P/gCjOlbTyzOxfv0+1jaQvbn2vrAXxKtQ9YEuE 8Bm6vg/mpddWPKWAXtQYvZAAXyyaDFAPAXSqRvmtDr+vbLo6QZFtfcAUKDFJM92jAJKR eYgLda4fMoaebv2Db/XpxgqZnyjHm1Nxa5LN9PYr95VOlbFw06R7WZm21E+pnk2udcaz EbidlvjaWg8RdS0Hbn5LOlWZVl0qGUoJtPt2l5j8QbGm1JVTfCvSJSlZS/fyA24ebLDZ SdBw== X-Gm-Message-State: AIkVDXJZF7RprrtvrLnyHuc9Z4FXrq2km9uIYHH9bOyPhfRkTb8wGrIbhBKZJ9Nu7ND0tSgE X-Received: by 10.98.33.66 with SMTP id h63mr1099509pfh.142.1484016443398; Mon, 09 Jan 2017 18:47:23 -0800 (PST) Received: from ruslan-mbp.purestorage.com ([64.84.70.252]) by smtp.gmail.com with ESMTPSA id p1sm568211pgc.29.2017.01.09.18.47.22 for (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Jan 2017 18:47:22 -0800 (PST) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 7.3 \(1878.6\)) From: Ruslan Nikolaev In-Reply-To: <56D73D38-A0F0-4289-BEF2-A46620461E94@purestorage.com> Date: Mon, 9 Jan 2017 18:47:16 -0800 Content-Transfer-Encoding: quoted-printable Message-Id: References: <56D73D38-A0F0-4289-BEF2-A46620461E94@purestorage.com> To: dev@dpdk.org X-Mailer: Apple Mail (2.1878.6) Subject: Re: [dpdk-dev] MSI-X vector #1 seems to be stalled sometimes after VF reset (ixgbe) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2017 02:47:24 -0000 interrupts_excerpts.patch: drivers/net/ixgbe/ixgbe_ethdev.c eth_ixgbevf_dev_init: @@ -1462,8 +1467,9 @@ rte_intr_callback_register(&pci_dev->intr_handle, ixgbevf_dev_interrupt_handler, (void *)eth_dev); - rte_intr_enable(&pci_dev->intr_handle); - ixgbevf_intr_enable(hw); + + /* XXX: not enabling interrupts here since they are enabled in = dev_start anyway, + and we do not have correct number of interrupt vectors here = yet. */ PMD_INIT_LOG(DEBUG, "port %d vendorID=3D0x%x deviceID=3D0x%x = mac.type=3D%s", eth_dev->data->port_id, pci_dev->id.vendor_id, ixgbevf_dev_start: @@ -4168,7 +4174,7 @@ /* check and configure queue intr-vector mapping */ if (dev->data->dev_conf.intr_conf.rxq !=3D 0) { - intr_vector =3D dev->data->nb_rx_queues; + intr_vector =3D 1; if (rte_intr_efd_enable(intr_handle, intr_vector)) return -1; } @@ -4789,31 +4801,27 @@ static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t = queue_id) { - uint32_t mask; + /* use vector #0 for mailbox interrupts and vector #1 for all RX = queues */ + uint8_t idx =3D (queue_id < IXGBE_MAX_QUEUE_NUM_PER_VF); + uint32_t mask =3D 1U << idx; struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); - mask =3D IXGBE_READ_REG(hw, IXGBE_VTEIMS); - mask |=3D (1 << IXGBE_MISC_VEC_ID); - RTE_SET_USED(queue_id); IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask); - rte_intr_enable(&dev->pci_dev->intr_handle); - return 0; } static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t = queue_id) { - uint32_t mask; + /* use vector #0 for mailbox interrupts and vector #1 for all RX = queues */ + uint8_t idx =3D (queue_id < IXGBE_MAX_QUEUE_NUM_PER_VF); + uint32_t mask =3D 1U << idx; struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); - mask =3D IXGBE_READ_REG(hw, IXGBE_VTEIMS); - mask &=3D ~(1 << IXGBE_MISC_VEC_ID); - RTE_SET_USED(queue_id); - IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask); + IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, mask); return 0; } ixgbevf_configure_msix: @@ -4948,10 +4956,9 @@ struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); uint32_t q_idx; - uint32_t vector_idx =3D IXGBE_MISC_VEC_ID; /* Configure VF other cause ivar */ - ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); + ixgbevf_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); /* won't configure msix register if no mapping is done * between intr vector and event fd. @@ -4961,11 +4968,9 @@ /* Configure all RX queues of VF */ for (q_idx =3D 0; q_idx < dev->data->nb_rx_queues; q_idx++) { - /* Force all queue use vector 0, - * as IXGBE_VF_MAXMSIVECOTR =3D 1 - */ - ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); - intr_handle->intr_vec[q_idx] =3D vector_idx; + /* Force all queues to use vector 1 */ + ixgbevf_set_ivar_map(hw, 0, q_idx, IXGBE_RX_VEC_START); + intr_handle->intr_vec[q_idx] =3D IXGBE_RX_VEC_START; } }