From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id F22E31B3B1 for ; Sat, 13 Oct 2018 03:56:18 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Oct 2018 18:56:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,374,1534834800"; d="scan'208";a="81089764" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga008.jf.intel.com with ESMTP; 12 Oct 2018 18:56:17 -0700 Received: from fmsmsx154.amr.corp.intel.com (10.18.116.70) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 12 Oct 2018 18:56:17 -0700 Received: from fmsmsx151.amr.corp.intel.com ([169.254.7.87]) by FMSMSX154.amr.corp.intel.com ([169.254.6.126]) with mapi id 14.03.0319.002; Fri, 12 Oct 2018 18:56:16 -0700 From: "Wang, Yipeng1" To: Honnappa Nagarahalli , "Richardson, Bruce" , "De Lara Guarch, Pablo" CC: "dev@dpdk.org" , "dharmik.thakkar@arm.com" , "gavin.hu@arm.com" , "nd@arm.com" , "Gobriel, Sameh" Thread-Topic: [PATCH v3 4/7] hash: add memory ordering to avoid race conditions Thread-Index: AQHUYfVdN2IJTatbZUOC3+ictwyaQaUcYh5A Date: Sat, 13 Oct 2018 01:56:15 +0000 Message-ID: References: <1539325918-125438-1-git-send-email-honnappa.nagarahalli@arm.com> <1539325918-125438-5-git-send-email-honnappa.nagarahalli@arm.com> In-Reply-To: <1539325918-125438-5-git-send-email-honnappa.nagarahalli@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOGUyMDAxOTItNjliNS00OWIzLTljYzktNmJlZjFhM2ZjZTg5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiUzJ3T1lFb0xEQktIMlFPUnc2WGlvT0FcL1hTdGlsWkZZR1RNMmJpNjNCenJXTjVuZkdkaWpDdms1K1wvQlwvOXFkQyJ9 x-originating-ip: [10.1.200.107] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3 4/7] hash: add memory ordering to avoid race conditions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 13 Oct 2018 01:56:19 -0000 When I applied this commit: fatal: sha1 information is lacking or useless (lib/librte_hash/rte_cuckoo_h= ash.c). Please double check. >-----Original Message----- >From: Honnappa Nagarahalli [mailto:honnappa.nagarahalli@arm.com] >Sent: Thursday, October 11, 2018 11:32 PM >To: Richardson, Bruce ; De Lara Guarch, Pablo = >Cc: dev@dpdk.org; Wang, Yipeng1 ; honnappa.nagarah= alli@arm.com; dharmik.thakkar@arm.com; >gavin.hu@arm.com; nd@arm.com >Subject: [PATCH v3 4/7] hash: add memory ordering to avoid race conditions > >Only race condition that can occur is - using the key store element >before the key write is completed. Hence, while inserting the element >the release memory order is used. Any other race condition is caught >by the key comparison. Memory orderings are added only where needed. >For ex: reads in the writer's context do not need memory ordering >as there is a single writer. [Wang, Yipeng]=20 I remember we discussed that this commit itself does not fix any bug/issue,= or enabling feature, it is supposed to work with the following patches to enable lock-free read-write concurrency. You separated the commits for e= asier review. If you plan to merge these commits and change the commit message it would b= e fine. Otherwise the current message title and content Is misleading. It sounds like a bug fix but actually not.