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X-Microsoft-Antispam-Message-Info: qq5yR+AnCeSy1R4is8FkWyVY5rtxIqmHdGLPXTYnlYyjihZIVWFP7f4PObUQoX7EFXxg7IYajG8P6zerXcG0keMvPGpi0VnJ1kiO6hE9AzG84fECNPfBdc51LGPALo/lwcymuirwqgmokBeGA69w+NqSN3p3WmXE3PYLujAfSptWUDPXHtDLim2KcFN5KQAhttNXv2HLaAW97ZVrNjzttFMd+ei5lge7xXUcVM6J3pyQX7+M80SBZTD3g13R3Xzlz9vMDjHGyvRS6vMq2EL+NkBrLBHts3QFFnNMSluYGzHHhi8BFK+vk3L3nTW9VXp3/sXcA1CbGZ8uibAuXlk/mcGvhvDD+S3wtfT3hw4Vb8bYJUQQ6UQnEwHvf+nbrOcYLn8+tqXNUzsNoRKaXyvuqw== X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jun 2020 04:40:42.9942 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 01dfca8b-5cf8-4d7c-085c-08d81be6950d X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT049.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0802MB2199 Subject: Re: [dpdk-dev] [PATCH v5 4/4] eal/atomic: add wrapper for c11 atomic thread fence X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > Subject: [PATCH v5 4/4] eal/atomic: add wrapper for c11 atomic thread fen= ce >=20 > Provide a wrapper for __atomic_thread_fence built-in to support optimized > code for __ATOMIC_SEQ_CST memory order for x86 platforms. >=20 > Suggested-by: Honnappa Nagarahalli > Signed-off-by: Phil Yang > Reviewed-by: Ola Liljedahl > --- > lib/librte_eal/arm/include/rte_atomic_32.h | 6 ++++++ > lib/librte_eal/arm/include/rte_atomic_64.h | 6 ++++++ > lib/librte_eal/include/generic/rte_atomic.h | 6 ++++++ > lib/librte_eal/ppc/include/rte_atomic.h | 6 ++++++ > lib/librte_eal/x86/include/rte_atomic.h | 17 +++++++++++++++++ > 5 files changed, 41 insertions(+) >=20 > diff --git a/lib/librte_eal/arm/include/rte_atomic_32.h > b/lib/librte_eal/arm/include/rte_atomic_32.h > index 7dc0d06..dbe7cc6 100644 > --- a/lib/librte_eal/arm/include/rte_atomic_32.h > +++ b/lib/librte_eal/arm/include/rte_atomic_32.h > @@ -37,6 +37,12 @@ extern "C" { >=20 > #define rte_cio_rmb() rte_rmb() >=20 > +static __rte_always_inline void > +rte_atomic_thread_fence(int mo) > +{ > + __atomic_thread_fence(mo); > +} > + > #ifdef __cplusplus > } > #endif > diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h > b/lib/librte_eal/arm/include/rte_atomic_64.h > index 7b7099c..22ff8ec 100644 > --- a/lib/librte_eal/arm/include/rte_atomic_64.h > +++ b/lib/librte_eal/arm/include/rte_atomic_64.h > @@ -41,6 +41,12 @@ extern "C" { >=20 > #define rte_cio_rmb() asm volatile("dmb oshld" : : : "memory") >=20 > +static __rte_always_inline void > +rte_atomic_thread_fence(int mo) > +{ > + __atomic_thread_fence(mo); > +} > + > /*------------------------ 128 bit atomic operations -------------------= ------*/ >=20 > #if defined(__ARM_FEATURE_ATOMICS) || > defined(RTE_ARM_FEATURE_ATOMICS) diff --git > a/lib/librte_eal/include/generic/rte_atomic.h > b/lib/librte_eal/include/generic/rte_atomic.h > index e6ab15a..5b941db 100644 > --- a/lib/librte_eal/include/generic/rte_atomic.h > +++ b/lib/librte_eal/include/generic/rte_atomic.h > @@ -158,6 +158,12 @@ static inline void rte_cio_rmb(void); > asm volatile ("" : : : "memory"); \ > } while(0) >=20 > +/** > + * Synchronization fence between threads based on the specified > + * memory order. > + */ > +static inline void rte_atomic_thread_fence(int mo); > + > /*------------------------- 16 bit atomic operations -------------------= ------*/ >=20 > /** > diff --git a/lib/librte_eal/ppc/include/rte_atomic.h > b/lib/librte_eal/ppc/include/rte_atomic.h > index 7e3e131..91c5f30 100644 > --- a/lib/librte_eal/ppc/include/rte_atomic.h > +++ b/lib/librte_eal/ppc/include/rte_atomic.h > @@ -40,6 +40,12 @@ extern "C" { >=20 > #define rte_cio_rmb() rte_rmb() >=20 > +static __rte_always_inline void > +rte_atomic_thread_fence(int mo) > +{ > + __atomic_thread_fence(mo); > +} > + > /*------------------------- 16 bit atomic operations -------------------= ------*/ > /* To be compatible with Power7, use GCC built-in functions for 16 bit > * operations */ > diff --git a/lib/librte_eal/x86/include/rte_atomic.h > b/lib/librte_eal/x86/include/rte_atomic.h > index b9dcd30..bd256e7 100644 > --- a/lib/librte_eal/x86/include/rte_atomic.h > +++ b/lib/librte_eal/x86/include/rte_atomic.h > @@ -83,6 +83,23 @@ rte_smp_mb(void) >=20 > #define rte_cio_rmb() rte_compiler_barrier() >=20 > +/** > + * Synchronization fence between threads based on the specified > + * memory order. > + * > + * On x86 the __atomic_thread_fence(__ATOMIC_SEQ_CST) generates > + * full 'mfence' which is quite expensive. The optimized > + * implementation of rte_smp_mb is used instead. > + */ > +static __rte_always_inline void > +rte_atomic_thread_fence(int mo) > +{ > + if (mo =3D=3D __ATOMIC_SEQ_CST) > + rte_smp_mb(); > + else > + __atomic_thread_fence(mo); > +} I think __ATOMIC_SEQ_CST needs to be used rarely. IMO, rte_atomic_thread_fe= nce should be called only for __ATOMIC_SEQ_CST memory order. For all others= the __atomic_thread_fence can be used directly. This will help us to stick= to using the atomic built-ins in most of the cases. Konstantin, is this ok for you? > + > /*------------------------- 16 bit atomic operations -------------------= ------*/ >=20 > #ifndef RTE_FORCE_INTRINSICS > -- > 2.7.4