From: Shahaf Shuler <shahafs@mellanox.com>
To: Yongseok Koh <yskoh@mellanox.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH] net/mlx5: add 128B padding of Rx completion entry
Date: Sun, 28 Oct 2018 13:55:46 +0000 [thread overview]
Message-ID: <DB7PR05MB4426819F6B2D521D86247D41C3F20@DB7PR05MB4426.eurprd05.prod.outlook.com> (raw)
In-Reply-To: <20181025062351.10135-1-yskoh@mellanox.com>
Thursday, October 25, 2018 9:24 AM, Yongseok Koh:
> Subject: [PATCH] net/mlx5: add 128B padding of Rx completion entry
>
> A PMD parameter (rxq_cqe_pad_en) is added to enable 128B padding of
> CQE on RX side. The size of CQE is aligned with the size of a cacheline of the
> core. If cacheline size is 128B, the CQE size is configured to be 128B even
> though the device writes only 64B data on the cacheline. This is to avoid
> unnecessary cache invalidation by device's two consecutive writes on to one
> cacheline. However in some architecture, it is more beneficial to update
> entire cacheline with padding the rest 64B rather than striding because read-
> modify-write could drop performance a lot. On the other hand, writing extra
> data will consume more PCIe bandwidth and could also drop the maximum
> throughput. It is recommended to empirically set this parameter. Disabled by
> default.
>
> Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Applied to next-net-mlx, thanks.
prev parent reply other threads:[~2018-10-28 13:55 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-25 6:24 Yongseok Koh
2018-10-28 13:55 ` Shahaf Shuler [this message]
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