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Thu, 17 Jan 2019 08:49:04 +0000 From: "Gavin Hu (Arm Technology China)" To: Gage Eads , "dev@dpdk.org" CC: "olivier.matz@6wind.com" , "arybchenko@solarflare.com" , "bruce.richardson@intel.com" , "konstantin.ananyev@intel.com" , Honnappa Nagarahalli Thread-Topic: [dpdk-dev] [PATCH v2 1/2] eal: add 128-bit cmpset (x86-64 only) Thread-Index: AQHUrSJoKFD1BchWBki9OtDxKYLlAqWzIv3Q Date: Thu, 17 Jan 2019 08:49:03 +0000 Message-ID: References: <20190110205538.24435-1-gage.eads@intel.com> <20190115223232.31866-1-gage.eads@intel.com> <20190115223232.31866-2-gage.eads@intel.com> In-Reply-To: <20190115223232.31866-2-gage.eads@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Gavin.Hu@arm.com; x-originating-ip: [113.29.88.7] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DB7PR08MB3228; 6:PfzYv3haKPCnNmZLD1J6jyjf1TROt74So7Nm3H+GZVgAy2C99uFROp9dQWpBvS6nOD8x53AjT82pByTizT5MyTmEanj0U3nSZfKUA/OOSQ2OswofFZ7sdcskc89/WK7bZy2JLAZzjKTMbUnrnCv62BaboRKjHGTIjJ2k02HQ0WWL6QMqherrfHX962fNUaA1JoDcQWUP64v/l5+nAKrsRdvklmGqPIKfClCtaZ6WSoiI59jAqwv3PimaTIie3RJx/+UvhFbovkkOsJuHDDxnub1JdN3sT7p05k5RuOuWfa6yiT3uBf91RFgIPo/gqY1Cbbky5Ul7Rw+XzgISmS4JcAOX3PNIidyelxOkIVch9MzGjZMll9usJyLCxo528qnchQfAgKZckC0uleNdu8tgeK3x8Mj4xgHD3sa4LLJU1Qr5Cig0ksWOszfMpJvpPeGLVreFD6/+dRnk094ATBwQwQ==; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB7PR08MB3228; H:DB7PR08MB3163.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: bgVndzipdj84qdYOEGBlVtyTz9uC8MHTX3AM5dSHAOELb6tkzZPbl180zFryJJbRlgsfBMjLFyLfT7om1l7BRwmlBVCB0UOBmVUAc/Nw6wxxgZkPmj7OEvLAIoE0lQgbBEAdGldzOA6ocjZWBhGvYs726JGAdls8V93+RPrWz6eW5uWwXazghgj7pnDFaujwrDvB1r57BzdaRJRv08+Oms3CtDI1x5qq4iy5PcGtpIy9G0w9Wpzte9ju4I9xLQba0K7FHURf+E6E9tNAc68AetgQ9VjLm4dLUlhaCxDuf2bshEkX5W0nnFf56jwN5vXiaC6lO1HW8C1mWF/7VrkK8gZ0oSA3qqVH5jUtD0NyvH9VB2o0Q9KzkgQpfNiz66fBqFHdNjjXaQC2pEUfMCDpuCNWEN07pS6iWaAejCQZEgI= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6f59c952-dcff-446b-514a-08d67c58a238 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jan 2019 08:49:03.9549 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR08MB3228 Subject: Re: [dpdk-dev] [PATCH v2 1/2] eal: add 128-bit cmpset (x86-64 only) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Jan 2019 08:49:05 -0000 > -----Original Message----- > From: dev On Behalf Of Gage Eads > Sent: Wednesday, January 16, 2019 6:33 AM > To: dev@dpdk.org > Cc: olivier.matz@6wind.com; arybchenko@solarflare.com; > bruce.richardson@intel.com; konstantin.ananyev@intel.com > Subject: [dpdk-dev] [PATCH v2 1/2] eal: add 128-bit cmpset (x86-64 only) > > This operation can be used for non-blocking algorithms, such as a > non-blocking stack or ring. > > Signed-off-by: Gage Eads > --- > .../common/include/arch/x86/rte_atomic_64.h | 22 > ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > index fd2ec9c53..34c2addf8 100644 > --- a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > @@ -34,6 +34,7 @@ > /* > * Inspired from FreeBSD src/sys/amd64/include/atomic.h > * Copyright (c) 1998 Doug Rabson > + * Copyright (c) 2019 Intel Corporation > * All rights reserved. > */ > > @@ -208,4 +209,25 @@ static inline void > rte_atomic64_clear(rte_atomic64_t *v) > } > #endif > > +static inline int > +rte_atomic128_cmpset(volatile uint64_t *dst, uint64_t *exp, uint64_t > *src) > +{ > +uint8_t res; > + > +asm volatile ( > + MPLOCKED > + "cmpxchg16b %[dst];" > + " sete %[res]" > + : [dst] "=3Dm" (*dst), > +[res] "=3Dr" (res) > + : "c" (src[1]), > +"b" (src[0]), > +"m" (*dst), > +"d" (exp[1]), > +"a" (exp[0]) > + : "memory"); > + > +return res; > +} > + CONFIG_RTE_DRIVER_MEMPOOL_NB_STACK=3Dy can't coexist with RTE_FORCE_INTRINS= ICS=3Dy, this should be explicitly described somewhere in the configuration= and documentations. > #endif /* _RTE_ATOMIC_X86_64_H_ */ > -- > 2.13.6 IMPORTANT NOTICE: The contents of this email and any attachments are confid= ential and may also be privileged. If you are not the intended recipient, p= lease notify the sender immediately and do not disclose the contents to any= other person, use it for any purpose, or store or copy the information in = any medium. Thank you.