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Thu, 17 Jan 2019 15:57:08 +0000 From: "Gavin Hu (Arm Technology China)" To: "Eads, Gage" , "dev@dpdk.org" CC: "olivier.matz@6wind.com" , "arybchenko@solarflare.com" , "Richardson, Bruce" , "Ananyev, Konstantin" , Honnappa Nagarahalli , nd Thread-Topic: [dpdk-dev] [PATCH v2 1/2] eal: add 128-bit cmpset (x86-64 only) Thread-Index: AQHUrSJoKFD1BchWBki9OtDxKYLlAqWzIv3QgABwJWCAAAuskA== Date: Thu, 17 Jan 2019 15:57:08 +0000 Message-ID: References: <20190110205538.24435-1-gage.eads@intel.com> <20190115223232.31866-1-gage.eads@intel.com> <20190115223232.31866-2-gage.eads@intel.com> <9184057F7FC11744A2107296B6B8EB1E541C84A3@FMSMSX108.amr.corp.intel.com> In-Reply-To: <9184057F7FC11744A2107296B6B8EB1E541C84A3@FMSMSX108.amr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Gavin.Hu@arm.com; x-originating-ip: [113.29.88.7] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: hr5yr4cOUu6bdjMaLHv2ceWqzl/YMsYvL3gOtes49IKnUbifnvxwlqyUOWfBgm3i0+V+vcPqJSNVQf80BjK7rnNoVkp7MCIvylyBvHFu5ZWbQMNHQn27UqhlvEeQD3JrgP2wtUNM9dWBGuJFMPJ6WfeU6UMjq1vLDTFEij/h/jrBt5KLDNz1uyMBF5fW0YZP395HQJSbD4+EMSOJ5nDJr9+qZpYao+CWdR6wM6BN9Rs6Sd7HV2gq3SYxjSlMphdi/87qPiAVYiP1Bw5yxsIMAJG7hsmjf3+LdxS5upJ6BEK702u8x4VSZoe1xRY8doKdIp+SVMqb+x/P6KIz94yyzsihM8TKck4wJh7NHE+qgAhxvEUQU6iXTGafZ2cMKlu/sS2hAqUhSun+y9hXbFO7tQmyzUVxGSD5iNLj19ZbZ6I= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 89774ea9-51c9-4756-e2f1-08d67c946f93 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jan 2019 15:57:08.7430 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR08MB3802 Subject: Re: [dpdk-dev] [PATCH v2 1/2] eal: add 128-bit cmpset (x86-64 only) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Jan 2019 15:57:10 -0000 > -----Original Message----- > From: Eads, Gage > Sent: Thursday, January 17, 2019 11:14 PM > To: Gavin Hu (Arm Technology China) ; > dev@dpdk.org > Cc: olivier.matz@6wind.com; arybchenko@solarflare.com; Richardson, > Bruce ; Ananyev, Konstantin > ; Honnappa Nagarahalli > > Subject: RE: [dpdk-dev] [PATCH v2 1/2] eal: add 128-bit cmpset (x86-64 > only) >=20 >=20 >=20 > > -----Original Message----- > > From: Gavin Hu (Arm Technology China) [mailto:Gavin.Hu@arm.com] > > Sent: Thursday, January 17, 2019 2:49 AM > > To: Eads, Gage ; dev@dpdk.org > > Cc: olivier.matz@6wind.com; arybchenko@solarflare.com; Richardson, > Bruce > > ; Ananyev, Konstantin > > ; Honnappa Nagarahalli > > > > Subject: RE: [dpdk-dev] [PATCH v2 1/2] eal: add 128-bit cmpset (x86-64 > only) > > > > > > > > > -----Original Message----- > > > From: dev On Behalf Of Gage Eads > > > Sent: Wednesday, January 16, 2019 6:33 AM > > > To: dev@dpdk.org > > > Cc: olivier.matz@6wind.com; arybchenko@solarflare.com; > > > bruce.richardson@intel.com; konstantin.ananyev@intel.com > > > Subject: [dpdk-dev] [PATCH v2 1/2] eal: add 128-bit cmpset (x86-64 > > > only) > > > > > > This operation can be used for non-blocking algorithms, such as a > > > non-blocking stack or ring. > > > > > > Signed-off-by: Gage Eads > > > --- > > > .../common/include/arch/x86/rte_atomic_64.h | 22 > > > ++++++++++++++++++++++ > > > 1 file changed, 22 insertions(+) > > > > > > diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > > > b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > > > index fd2ec9c53..34c2addf8 100644 > > > --- a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > > > +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > > > @@ -34,6 +34,7 @@ > > > /* > > > * Inspired from FreeBSD src/sys/amd64/include/atomic.h > > > * Copyright (c) 1998 Doug Rabson > > > + * Copyright (c) 2019 Intel Corporation > > > * All rights reserved. > > > */ > > > > > > @@ -208,4 +209,25 @@ static inline void > > > rte_atomic64_clear(rte_atomic64_t *v) } #endif > > > > > > +static inline int > > > +rte_atomic128_cmpset(volatile uint64_t *dst, uint64_t *exp, uint64_t > > > *src) > > > +{ > > > +uint8_t res; > > > + > > > +asm volatile ( > > > + MPLOCKED > > > + "cmpxchg16b %[dst];" > > > + " sete %[res]" > > > + : [dst] "=3Dm" (*dst), > > > +[res] "=3Dr" (res) > > > + : "c" (src[1]), > > > +"b" (src[0]), > > > +"m" (*dst), > > > +"d" (exp[1]), > > > +"a" (exp[0]) > > > + : "memory"); > > > + > > > +return res; > > > +} > > > + > > > > CONFIG_RTE_DRIVER_MEMPOOL_NB_STACK=3Dy can't coexist with > > RTE_FORCE_INTRINSICS=3Dy, this should be explicitly described somewhere > in the > > configuration and documentations. > > >=20 > This patch places rte_atomic128_cmpset() outside of the > RTE_FORCE_INTRINSICS ifndef, and this file is included regardless of that > config flag, so it's compiled either way. >=20 Acked-by: Gavin Hu > > > #endif /* _RTE_ATOMIC_X86_64_H_ */ > > > -- > > > 2.13.6 > >