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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0802MB2232 Subject: Re: [dpdk-dev] [PATCH v2 1/2] virtio: one way barrier for split vring used idx X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > > > Subject: Re: [dpdk-dev] [PATCH v2 1/2] virtio: one way barrier for=20 > > > split vring used idx > > > > > > On Thu, 2 Apr 2020 10:57:52 +0800 > > > Joyce Kong wrote: > > > > > > > -(vq)->vq_used_cons_idx)) > > > > +static inline uint16_t > > > > +virtqueue_nused(struct virtqueue *vq) > > > vq is unmodified and should be const > > > > > > > +{ > > > > +uint16_t idx; > > > > +if (vq->hw->weak_barriers) { > > > Put blank line between declaration and if statement > > Will fix in v3. > > > > > > > +/* x86 prefers to using rte_smp_rmb over __atomic_load_n as it=20 > > > > +reports > > > > + * a slightly better perf, which comes from the saved branch by=20 > > > > +the > > > compiler. > > > > + * The if and else branches are identical with the smp and cio=20 > > > > + barriers > > > both > > > > + * defined as compiler barriers on x86. > > > > + */ > > > > > > Do not put comments on left margin (except in function prolog). > > Will fix in v3. > > > > > > > +#ifdef RTE_ARCH_X86_64 > > > > +idx =3D vq->vq_split.ring.used->idx; rte_smp_rmb(); #else idx =3D= =20 > > > +__atomic_load_n(&(vq)->vq_split.ring.used->idx, > > > > +__ATOMIC_ACQUIRE); > > > > +#endif > > > > +} else { > > > > +idx =3D vq->vq_split.ring.used->idx; rte_cio_rmb(); } return (idx = -=20 > > > > +vq->vq_used_cons_idx); > > > > > > Parenthesis around arguments to return are unnecessary. > > > BSD code likes it, Linux style does not. > > Will fix in v3. > > > > > > > +} > > > > > > This kind of arch specific code is hard to maintain. > > > Does it really make that much difference. > > Yes, a stronger than required barrier is a performance killer,=20 > > especially in the fast path. > > The test was conducted on the ThunderX2+Intel XL710 testbed, the PVP=20 > > test case. > > /Gavin > I think if the performance deference is not much we should stay with C11 = built-ins for x86. How much is the=20 > performance difference on x86? According to intel's PVP test for packed ring, ~1.5% perf loss would be cau= sed on x86 if staying with __atomic_load_n. So rte_smp_rmb is kept for x86 = in packed ring patches which have been merged and the similar change is don= e in split ring patches.