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Tue, 12 Feb 2019 08:50:43 +0000 From: "Phil Yang (Arm Technology China)" To: Pavan Nikhilesh Bhagavatula , "jerinj@marvell.com" , "Gavin Hu (Arm Technology China)" , "bruce.richardson@intel.com" , "thomas@monjalon.net" CC: "dev@dpdk.org" , nd , nd Thread-Topic: [dpdk-dev] [PATCH v4 4/5] config: add octeontx2 machine config Thread-Index: AQHUqAe8rmlSY6l9sU+oH5LbckYvz6XcCsjA Date: Tue, 12 Feb 2019 08:50:43 +0000 Message-ID: References: <20190106131933.7898-1-jerinj@marvell.com> <20190109103915.29210-1-pbhagavatula@marvell.com> <20190109103915.29210-4-pbhagavatula@marvell.com> In-Reply-To: <20190109103915.29210-4-pbhagavatula@marvell.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Phil.Yang@arm.com; x-originating-ip: [113.29.88.7] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DB7PR08MB3097; 20:YFWibjuP1vEbJBjM3liISKWJ/CeErvBN4So7GDv5P/dhsARQjCbZOXH14tKHi4VNUm3ROgG0pjiJ8zHOYsOp5dj7Gd/j8/SNxD5u1lROR8cylaPnjKZivPef7GvyrbP++If/6exfHk2MSUUqhiFSB2R8IsujYq2RKAXtiNOylKA= x-ms-office365-filtering-correlation-id: 066df3e2-0742-4988-15f9-08d690c72c86 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB7PR08MB3097; H:DB7PR08MB3385.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: sUeFqObBR6OtsVLNrs2guoxw+8c/NBu1H/YCxW+d7KdM0ld02jQtI4w0d5kyaLxFUN63Mid86ycBWp7O7fdbjGDNu7iw6lQqpPQajCJAsdek9dOQgp0A3oHMuC5T1p+SDNLWFq0Hv7hASqHRDievYF6E+B0D7kq60p0iEAejyuP0miGms7WaxTtz6KO4yJZwPWK8gvajXzlllJvv4cDNXVAgFcsIlHTOZf6icMP2UX0AUTLkeWOEU1RGqSaR5q+86YHtW/Eqe/c3najgh2EQ1KJhE56mpfxSd3/jzAD8JuER6ZGvdUaBHjEImMrY137DzPJc0nE43QcVCbheKVIldOP0EHSkez3pGONy3ZIj6nW8VMJOcGuvZSXmKzAmSbkR+puCriFPRo5AQTeJw5gbXFvhscu0CGzqiAiRd70ZdMA= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 066df3e2-0742-4988-15f9-08d690c72c86 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Feb 2019 08:50:43.7689 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR08MB3097 Subject: Re: [dpdk-dev] [PATCH v4 4/5] config: add octeontx2 machine config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Feb 2019 08:50:46 -0000 Hi Jerin/Pavan, > -----Original Message----- > From: dev On Behalf Of Pavan Nikhilesh Bhagavatula > Sent: Wednesday, January 9, 2019 6:40 PM > To: jerinj@marvell.com; Gavin Hu (Arm Technology China) > ; bruce.richardson@intel.com; thomas@monjalon.net > Cc: dev@dpdk.org; Pavan Nikhilesh Bhagavatula > Subject: [dpdk-dev] [PATCH v4 4/5] config: add octeontx2 machine config >=20 > From: Jerin Jacob >=20 > Optimized configuration for Marvell octeontx2 SoC. Update meson build to > support Marvell octeontx2 SoC. >=20 > Signed-off-by: Jerin Jacob > Signed-off-by: Pavan Nikhilesh > --- > config/arm/meson.build | 10 +++++- > config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++ > mk/machine/octeontx2/rte.vars.mk | 34 +++++++++++++++++++ > 3 files changed, 61 insertions(+), 1 deletion(-) create mode 100644 > config/defconfig_arm64-octeontx2-linuxapp-gcc > create mode 100644 mk/machine/octeontx2/rte.vars.mk >=20 > diff --git a/config/arm/meson.build b/config/arm/meson.build index > aca285b6a..8086357a1 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -60,6 +60,13 @@ flags_thunderx2_extra =3D [ > ['RTE_MAX_NUMA_NODES', 2], > ['RTE_MAX_LCORE', 256], > ['RTE_USE_C11_MEM_MODEL', true]] > +flags_octeontx2_extra =3D [ > + ['RTE_MACHINE', '"octeontx2"'], > + ['RTE_MAX_NUMA_NODES', 1], > + ['RTE_MAX_LCORE', 24], > + ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false], > + ['RTE_LIBRTE_VHOST_NUMA', false], > + ['RTE_EAL_IGB_UIO', false]] >=20 > machine_args_generic =3D [ > ['default', ['-march=3Darmv8-a+crc+crypto']], @@ -77,7 +84,8 @@ > machine_args_cavium =3D [ > ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], > ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], > ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra], > - ['0xaf', ['-mcpu=3Dthunderx2t99'], flags_thunderx2_extra]] > + ['0xaf', ['-mcpu=3Dthunderx2t99'], flags_thunderx2_extra], > + ['0xb2', ['-mcpu=3Docteontx2'], flags_octeontx2_extra]] >=20 > ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) > impl_generic =3D ['Generic armv8', flags_generic, machine_args_generic] d= iff --git > a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64- > octeontx2-linuxapp-gcc > new file mode 100644 > index 000000000..9a99eada1 > --- /dev/null > +++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc > @@ -0,0 +1,18 @@ > +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Marvell > +International Ltd # > + > +#include "defconfig_arm64-armv8a-linuxapp-gcc" > + > +CONFIG_RTE_MACHINE=3D"octeontx2" > + > +CONFIG_RTE_CACHE_LINE_SIZE=3D128 > +CONFIG_RTE_MAX_NUMA_NODES=3D1 > +CONFIG_RTE_MAX_LCORE=3D24 > + > +# Doesn't support NUMA > +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=3Dn > +CONFIG_RTE_LIBRTE_VHOST_NUMA=3Dn > + > +# Recommend to use VFIO as co-processors needs SMMU/IOMMU > +CONFIG_RTE_EAL_IGB_UIO=3Dn > diff --git a/mk/machine/octeontx2/rte.vars.mk > b/mk/machine/octeontx2/rte.vars.mk > new file mode 100644 > index 000000000..e209cf492 > --- /dev/null > +++ b/mk/machine/octeontx2/rte.vars.mk > @@ -0,0 +1,34 @@ > +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Marvell > +International Ltd # > + > +# > +# machine: > +# > +# - can define ARCH variable (overridden by cmdline value) > +# - can define CROSS variable (overridden by cmdline value) > +# - define MACHINE_CFLAGS variable (overridden by cmdline value) > +# - define MACHINE_LDFLAGS variable (overridden by cmdline value) > +# - define MACHINE_ASFLAGS variable (overridden by cmdline value) > +# - can define CPU_CFLAGS variable (overridden by cmdline value) that > +# overrides the one defined in arch. > +# - can define CPU_LDFLAGS variable (overridden by cmdline value) that > +# overrides the one defined in arch. > +# - can define CPU_ASFLAGS variable (overridden by cmdline value) that > +# overrides the one defined in arch. > +# - may override any previously defined variable > +# > + > +# ARCH =3D > +# CROSS =3D > +# MACHINE_CFLAGS =3D > +# MACHINE_LDFLAGS =3D > +# MACHINE_ASFLAGS =3D > +# CPU_CFLAGS =3D > +# CPU_LDFLAGS =3D > +# CPU_ASFLAGS =3D > + > +include $(RTE_SDK)/mk/rte.helper.mk > + > +MACHINE_CFLAGS +=3D $(call rte_cc_has_argument, > +-march=3Darmv8.2-a+crc+crypto+lse) MACHINE_CFLAGS +=3D $(call > +rte_cc_has_argument, -mcpu=3Docteontx2) Why do you choose to expose armv8.2-a flag other than using armv8a combine = with the extension flags here? The value 'armv8.2-a' implies 'armv8.1-a' and enables compiler support for = the ARMv8.2-A architecture extensions. And the 'lse' extension is the defau= lt feature for 'armv8.1-a'. So it seems there is no need to specify 'armv8.= 2-a' with 'lse'. According to the meson build code, the default -march config for Cavium is = 'armv8-a'. So I think it seems better to keep 'armv8-a' here and add flags = for the specific extensions. The same for thunderx2 configuration. > -- > 2.20.1 Thanks, Phil Yang