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Mon, 21 Sep 2020 10:22:01 +0000 Received: from DB7PR08MB3865.eurprd08.prod.outlook.com ([fe80::519c:72bd:e189:625b]) by DB7PR08MB3865.eurprd08.prod.outlook.com ([fe80::519c:72bd:e189:625b%7]) with mapi id 15.20.3391.024; Mon, 21 Sep 2020 10:22:01 +0000 From: Phil Yang To: "Jakub Grajciar -X (jgrajcia - PANTHEON TECH SRO at Cisco)" , Honnappa Nagarahalli , "dev@dpdk.org" CC: Ruifeng Wang , nd , nd , nd Thread-Topic: [PATCH] net/memif: relax barrier for zero copy path Thread-Index: AQHWjg37vRHCoe0/oEOVJngTp5ke0qly0BMAgAATLwA= Date: Mon, 21 Sep 2020 10:22:00 +0000 Message-ID: References: <1599802699-20876-1-git-send-email-phil.yang@arm.com> In-Reply-To: Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ts-tracking-id: 2722E3CE002B4E46A674A546519074AA.0 x-checkrecipientchecked: true Authentication-Results-Original: cisco.com; dkim=none (message not signed) header.d=none;cisco.com; dmarc=none action=none header.from=arm.com; x-originating-ip: [203.126.0.112] x-ms-publictraffictype: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 811e5f17-e47d-403c-87cd-08d85e1831d7 x-ms-traffictypediagnostic: DBBPR08MB4266:|AM6PR08MB4327: x-ms-exchange-transport-forked: True X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true nodisclaimer: true x-ms-oob-tlc-oobclassifiers: OLM:8882;OLM:8882; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(376002)(136003)(346002)(396003)(39860400002)(46966005)(356005)(82740400003)(81166007)(33656002)(47076004)(8676002)(5660300002)(52536014)(86362001)(26005)(7696005)(70206006)(70586007)(6506007)(8936002)(4326008)(83380400001)(336012)(54906003)(478600001)(9686003)(316002)(82310400003)(186003)(55016002)(2906002)(110136005); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Sep 2020 10:22:08.0210 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 811e5f17-e47d-403c-87cd-08d85e1831d7 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT022.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB4327 Subject: Re: [dpdk-dev] [PATCH] net/memif: relax barrier for zero copy path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Jakub Grajciar -X (jgrajcia - PANTHEON TECH SRO at Cisco) writes: > > Subject: RE: [PATCH] net/memif: relax barrier for zero copy path > > > > Hi Jakub, > > I am trying to review this patch. I am having difficulty in > understanding > > the implementation for the queue/ring, appreciate if you could help me > > understand the logic. >=20 > 'ring' refers to a ring buffer holding packet descriptors. These descript= ors > hold metadata about the packet (packet buffer address, length, etc..). > 'queues' are a representation of rings and buffers (+ some metadata). In > more detail, one ring (S2M) and packet buffers allocated for this ring wo= uld > be represented as 'tx queue' for the slave and 'rx queue' for the master. >=20 > > > > 1) The S2M queues - are used to send packets from slave to master. My > > understanding is that, the slave thread would call 'eth_memif_tx_zc' an= d > the > > master thread would call 'eth_memif_rx_zc'. Is this correct? > > 2) The M2S queues - are used to send packets from master to slave. Here > the > > slave thread would call 'eth_memif_rx_zc' and the master thread would c= all > > 'eth_memif_tx_zc'. Is this correct? >=20 > This is inded correct. =20 > > > > > > Using 'rte_mb' to synchronize the shared ring head/tail between > > > producer and consumer will stall the pipeline and damage performance > > > on the weak memory model platforms, such like aarch64. > > > > > > Relax the expensive barrier with c11 atomic with explicit memory > > > ordering can improve 3.6% performance on throughput. >=20 > My question here is: `rte_mb` is supposed to make sure that head/tail > pointer are not updated before the packets are written into shared memory= . > Does the atomic ensures that the packets are written into shared memory > before head/tail pointers are updated? Yes, it does.=20 The atomic store-release acts as a one-way barrier here to make sure all th= e memory accesses before the store-release are observed before it. Thanks, Phil